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DIRECT MEMORY ACCESS UNIT
Module
Timer 2
DMA Request
Internal - DMA
Inter-module
Request
Arbitration
Multiplexer
Logic
Timer 2
Timer 2 Request
Request
Source Pointer
Source Pointer
Destination Pointer
Destination Pointer
Channel 0
Channel 1
Control Logic
Control Logic
DRQ Pin
DRQ Pin
A1540-01
Figure 10-5. Two-Channel DMA Module
A higher-priority DMA channel will interrupt the transfers of a lower-priority channel. Figure
10-6 shows several transfers with different combinations of channel priority and synchronization.
10-10
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