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CHAPTER 9
TIMER/COUNTER UNIT
The Timer/Counter Unit can be used in many applications. Some of these applications include a
real-time clock, a square-wave generator and a digital one-shot. All of these can be implemented
in a system design. A real-time clock can be used to update time-dependent memory variables. A
square-wave generator can be used to provide a system clock tick for peripheral devices. (See
"Timer/Counter Unit Application Examples" on page 9-17 for code examples that configure the
Timer/Counter Unit for these applications.)
9.1
FUNCTIONAL OVERVIEW
The Timer/Counter Unit is composed of three independent 16-bit timers (see Figure 9-1). The op-
eration of these timers is independent of the CPU. The internal Timer/Counter Unit can be mod-
eled as a single counter element, time-multiplexed to three register banks. The register banks are
dual-ported between the counter element and the CPU. During a given bus cycle, the counter el-
ement and CPU can both access the register banks; these accesses are synchronized.
The Timer/Counter Unit is serviced over four clock periods, one timer during each clock, with an
idle clock at the end (see Figure 9-2). No connection exists between the counter element's se-
quencing through timer register banks and the Bus Interface Unit's sequencing through T-states.
Timer operation and bus interface operation are asynchronous. This time-multiplexed scheme re-
sults in a delay of 2½ to 6½ CLKOUT periods from timer input to timer output.
Each timer keeps its own running count and has a user-defined maximum count value. Timers 0
and 1 can use one maximum count value (single maximum count mode) or two alternating max-
imum count values (dual maximum count mode). Timer 2 can use only one maximum count val-
ue. The control register for each timer determines the counting mode to be used. When a timer is
serviced, its present count value is incremented and compared to the maximum count for that tim-
er. If these two values match, the count value resets to zero. The timers can be configured either
to stop after a single cycle or to run continuously.
Timers 0 and 1 are functionally identical. Figure 9-3 illustrates their operation. Each has a
latched, synchronized input pin and a single output pin. Each timer can be clocked internally or
externally. Internally, the timer can either increment at ¼ CLKOUT frequency or be prescaled by
Timer 2. A timer that is prescaled by Timer 2 increments when Timer 2 reaches its maximum
count value.
9-1
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