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13.1.4.3
Port 3 Organization
Port 3 consists of six pins: four output-only pins and two open-drain bidirectional pins. The four
output-only port pins are multiplexed with DMA and serial communications interrupt requests.
The two open-drain bidirectional pins are not multiplexed with a peripheral function. The multi-
plexing options for Port 3 are shown in Table 13-3.
Pin Name
P3.5
P3.4
P3.3/DMAI1
P3.2/DMAI0
P3.1/TXI1
P3.0/RXI1
NOTE: P3.5 and P3.4 float when configured as peripheral
13.2 PROGRAMMING THE I/O PORT UNIT
Each port is controlled by a set of four Peripheral Control Block registers: the Port Control Reg-
ister (PxCON), the Port Direction Register (PxDIR), the Port Data Latch Register (PxLTCH) and
the Port Pin State Register (PxPIN).
13.2.1 Port Control Register
The Port Control Register (Figure 13-4) selects the overall function for each port pin: peripheral
or port. For I/O ports, the Port Control Register is used to assign the pin to either the associated
on-chip peripheral or to a general-purpose I/O port. For output-only ports, the Port Control Reg-
ister selects the source of data for the pin: either an on-chip peripheral or the Port Data latch.
Table 13-3. Port 3 Multiplexing Options
Peripheral Function
None (Note)
None (Note)
DMAI1
DMAI0
TXI1
RXI1
pins.
INPUT/OUTPUT PORTS
Port Function
P3.5 (Open-drain)
P3.4 (Open-drain)
P3.3
P3.2
P3.1
P3.0
13-7
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