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2.1.6
Flags
The 80C186 Modular Core family has six status flags (see Figure 2-5) that the Execution Unit
posts as the result of arithmetic or logical operations. Program branch instructions allow a pro-
gram to alter its execution depending on conditions flagged by a prior operation. Different in-
structions affect the status flags differently, generally reflecting the following states:
•
If the Auxiliary Flag (AF) is set, there has been a carry out from the low nibble into the high
nibble or a borrow from the high nibble into the low nibble of an 8-bit quantity (low-order
byte of a 16-bit quantity). This flag is used by decimal arithmetic instructions.
•
If the Carry Flag (CF) is set, there has been a carry out of or a borrow into the high-order bit
of the instruction result (8- or 16-bit). This flag is used by instructions that add or subtract
multibyte numbers. Rotate instructions can also isolate a bit in memory or a register by
placing it in the Carry Flag.
•
If the Overflow Flag (OF) is set, an arithmetic overflow has occurred. A significant digit
has been lost because the size of the result exceeded the capacity of its destination location.
An Interrupt On Overflow instruction is available that will generate an interrupt in this
situation.
•
If the Sign Flag (SF) is set, the high-order bit of the result is a 1. Since negative binary
numbers are represented in standard two's complement notation, SF indicates the sign of
the result (0 = positive, 1 = negative).
•
If the Parity Flag (PF) is set, the result has even parity, an even number of 1 bits. This flag
can be used to check for data transmission errors.
•
If the Zero Flag (ZF) is set, the result of the operation is zero.
Additional control flags (see Figure 2-5) can be set or cleared by programs to alter processor op-
erations:
•
Setting the Direction Flag (DF) causes string operations to auto-decrement. Strings are
processed from high address to low address (or "right to left"). Clearing DF causes string
operations to auto-increment. Strings are processed from low address to high address (or
"left to right").
•
Setting the Interrupt Enable Flag (IF) allows the CPU to recognize maskable external or
internal interrupt requests. Clearing IF disables these interrupts. The Interrupt Enable Flag
has no effect on software interrupts or non-maskable interrupts.
•
Setting the Trap Flag (TF) bit puts the processor into single-step mode for debugging. In
this mode, the CPU automatically generates an interrupt after each instruction. This allows
a program to be inspected instruction by instruction during execution.
The status and control flags are contained in a 16-bit Processor Status Word (see Figure 2-5). Re-
set initializes the Processor Status Word to 0F000H.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2-7
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