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8.3.2
Interrupt Requests
The processing of an external interrupt begins with the assertion of an interrupt request signal on
one of the IR lines. The signal first passes through the edge/level detection circuitry, then moves
on to the Interrupt Request Register.
8.3.2.1
Edge and Level Triggering
The IR lines are programmable for either edge or level triggering. Both types of triggering are
active high. For both types, the high state on the IR line must be maintained until after the falling
edge of the first INTA pulse during an interrupt acknowledge cycle. (See "Spurious Interrupts"
on page 8-10.)
Edge triggering is defined as a zero-to-one transition on an IR line. The high state on the IR line
must be maintained until after the falling edge of the first INTA pulse during an interrupt ac-
knowledge cycle. An edge-sensitive IR line must be returned to its low state for a specified
amount of time (refer to the data sheet for the value) to reset the edge detection circuit. Unless an
edge-sensitive IR line is returned to a low state after it is acknowledged, it cannot generate addi-
tional interrupts.
Level triggering is defined as a valid logic one on an IR line. The high value on the IR line must
be maintained until after the falling edge of the first INTA pulse during an interrupt acknowledge
cycle. Unlike an edge-sensitive IR line, a level-sensitive IR line continues to generate interrupts
as long as it is asserted. A level-sensitive IR signal must be deasserted before the EOI command
is issued if continuous interrupts from the same source are not desired.
8.3.2.2
The Interrupt Request Register
The Interrupt Request Register maintains one bit for each of the eight interrupt request lines.
When a valid interrupt request is present on an IR line, the corresponding Interrupt Request Reg-
ister bit is set (an interrupt is pending). The Interrupt Request Register bits are transparent; the
state of the IR line flows directly through the latch to the Priority Resolver until the bits are
latched. The output of the Interrupt Request Register is used by the Priority Resolver to decide
whether a CPU interrupt is warranted. Since the Interrupt Request Register is transparent, a tog-
gling IR line of sufficient priority causes the interrupt request output of the 8259A module to tog-
gle as well.
The state of Interrupt Request bits is latched by the falling edge of an internal signal called
FREEZE. FREEZE is valid between the falling edge of the first INTA pulse and the rising edge
of the last INTA pulse during an interrupt acknowledge cycle (see Figure 8-4). The highest-pri-
ority pending Interrupt Request Register bit is cleared on the first falling edge of INTA; the other
bits are left undisturbed.
INTERRUPT CONTROL UNIT
8-9
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