Bus Operation During Idle Mode - Intel 80C188EC User Manual

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CLOCK GENERATION AND POWER MANAGEMENT

CPU Core Clock

Figure 5-10. Entering Idle Mode

Bus Operation During Idle Mode

DMA requests, refresh requests and HOLD requests temporarily turn on the core clocks. If the

processor needs to run a DMA cycle during Idle mode, the internal core clock begins to toggle

on the falling CLKOUT edge three clocks after the processor samples the DMA request pin. After

one idle T-state, the processor runs the DMA cycle. The BIU uses the ready, wait state generation

and chip-select circuitry as necessary for DMA cycles during Idle mode. There is one idle T-state

after T4 before the internal core clock shuts off again.