Intel 80C188EC User Manual page 300

Both Requests Asserted
Channel 0
Priority Low Low
Synch SRC SRC
Channel 0
Priority High Low
Synch SRC SRC
Channel 0
Priority High Low
Synch Dest SRC
10.1.10.1.2 Rotating Priority
Channel priority rotates when the channels are programmed as both high or both low priority. The
highest priority is initially assigned to channel 1 of the module. After a channel performs a trans-
fer, it is assigned the lower priority. When requests are active for both channels, the transfers al-
ternate between the two.
10.1.10.1.3 The Internal DMA Request Multiplexer
The source of internal DMA requests for a module is selected by the Internal DMA Request Mul-
tiplexer. The multiplexer controls the routing of internal DMA requests to each channel of the
module. When the multiplexer is programmed to select Timer 2 DMA requests, the internal re-
quest line of each channel is connected to Timer 2. When the multiplexer is programmed to select
serial port DMA requests, channel 0 is connected to the transmitter DMA request and channel 1
is connected to the receiver DMA request. A simplified diagram of the Internal DMA Request
Multiplexer is shown in Figure 10-7.
It is important to note that the Internal DMA Request Multiplexer only selects the source of in-
ternal DMA requests; it does not control whether the channel responds to internal or external
DMA requests.
1
Channel 1 Channel 0 Channel 1 Channel 0
1
Channel 0 Channel 0
1
Channel 0 Channel 1
Destination Synch Releases Bus
Figure 10-6. Examples of DMA Priority
DIRECT MEMORY ACCESS UNIT
Channel 1 Channel 1
Channel 0 Completes
All Transfers
Channel 0 Channel 1
Etc.
Etc.
Etc.
A1190-0A
10-11