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INSTRUCTION SET DESCRIPTIONS
Name
IDIV
Integer Divide:
IDIV src
Performs a signed division of the
accumulator (and its extension) by the
source operand. If the source operand
is a byte, it is divided into the double-
length dividend assumed to be in
registers AL and AH; the single-length
quotient is returned in AL, and the
single-length remainder is returned in
AH. For byte integer division, the
maximum positive quotient is +127
(7FH) and the minimum negative
quotient is –127 (81H).
If the source operand is a word, it is
divided into the double-length dividend
in registers AX and DX; the single-
length quotient is returned in AX, and
the single-length remainder is returned
in DX. For word integer division, the
maximum positive quotient is +32,767
(7FFFH) and the minimum negative
quotient is –32,767 (8001H).
If the quotient is positive and exceeds
the maximum, or is negative and is
less than the minimum, the quotient
and remainder are undefined, and a
type 0 interrupt is generated. In
particular, this occurs if division by 0 is
attempted. Nonintegral quotients are
truncated (toward 0) to integers, and
the remainder has the same sign as
the dividend.
Instruction Operands:
IDIV reg
IDIV mem
NOTE: The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
C-16
Table C-4. Instruction Set (Continued)
Description
Operation
When Source Operand is a Byte:
(temp) ← (byte-src)
if
(temp) / (AX) > 0 and
(temp) / (AX) > 7FH or
(temp) / (AX) < 0 and
(temp) / (AX) < 0 – 7FH – 1
then (type 0 interrupt is generated)
(SP) ← (SP) – 2
((SP) + 1:(SP)) ← FLAGS
(IF) ← 0
(TF) ← 0
(SP) ← (SP) – 2
((SP) + 1:(SP)) ← (CS)
(CS) ← (2)
(SP) ← (SP) – 2
((SP) + 1:(SP)) ← (IP)
(IP) ← (0)
else
(AL) ← (temp) / (AX)
(AH) ← (temp) % (AX)
When Source Operand is a Word:
(temp) ← (word-src)
if
(temp) / (DX:AX) > 0 and
(temp) / (DX:AX) > 7FFFH or
(temp) / (DX:AX) < 0 and
(temp) / (DX:AX) < 0 – 7FFFH – 1
then (type 0 interrupt is generated)
(SP) ← (SP) – 2
((SP) + 1:(SP)) ← FLAGS
(IF) ← 0
(TF) ← 0
(SP) ← (SP) – 2
((SP) + 1:(SP)) ← (CS)
(CS) ← (2)
(SP) ← (SP) – 2
((SP) + 1:(SP)) ← (IP)
(IP) ← (0)
else
(AX) ← (temp) / (DX:AX)
(DX) ← (temp) % (DX:AX)
Flags
Affected
AF ?
CF ?
DF –
IF –
OF ?
PF ?
SF ?
TF –
ZF ?
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