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BUS INTERFACE UNIT
CLKOUT
RD/ WR
AD15:0
Write
AD15:0
Read
S2:0
NOTES:
1.
T
CLOV
2.
T
CLOV
3.
T
CLIS
4.
T
CLOV
5.
T
CLIH
6.
T
WHDX
7.
T
RHAV
3-14
T2
1
Valid Write Data
: Clock low to valid RD/ WR active; Write data valid
: Clock low to status inactive
: Data input valid to clock low
: Clock valid to RD/ WR inactive
: Data input HOLD from clock low
: Output data HOLD from WR high
: Bus no longer floating from RD high
Figure 3-12. Data Phase Signal Relationships
T3
or TW
4
2
5
3
Valid
Read Data
T4
or TI
6
7
A1103-0A
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