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80C186EC/80C188EC
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Summary of Contents for Intel 80C188EC

  • Page 1 80C186EC/80C188EC Microprocessor User’s Manual...
  • Page 2 80C186EC/80C188EC Microprocessor User’s Manual 1995 Order Number 272047-003...
  • Page 3 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
  • Page 4: Table Of Contents

    CONTENTS CHAPTER 1 INTRODUCTION HOW TO USE THIS MANUAL..................1-2 RELATED DOCUMENTS ....................1-3 ELECTRONIC SUPPORT SYSTEMS ................1-4 1.3.1 FaxBack Service .......................1-4 1.3.2 Bulletin Board System (BBS) ..................1-5 1.3.2.1 How to Find Ap BUILDER Software and Hypertext Documents on the BBS ...1-6 1.3.3 CompuServe Forums ....................1-6 1.3.4...
  • Page 5 CONTENTS INTERRUPTS AND EXCEPTION HANDLING ............2-39 2.3.1 Interrupt/Exception Processing ................2-39 2.3.1.1 Non-Maskable Interrupts ................2-42 2.3.1.2 Maskable Interrupts ..................2-42 2.3.1.3 Exceptions .....................2-42 2.3.2 Software Interrupts ....................2-44 2.3.3 Interrupt Latency .....................2-44 2.3.4 Interrupt Response Time ..................2-45 2.3.5 Interrupt and Exception Priority ................2-46 CHAPTER 3 BUS INTERFACE UNIT MULTIPLEXED ADDRESS AND DATA BUS ..............
  • Page 6 CONTENTS CHAPTER 4 PERIPHERAL CONTROL BLOCK PERIPHERAL CONTROL REGISTERS................ 4-1 PCB RELOCATION REGISTER..................4-1 RESERVED LOCATIONS ..................... 4-4 ACCESSING THE PERIPHERAL CONTROL BLOCK ..........4-4 4.4.1 Bus Cycles .......................4-4 4.4.2 READY Signals and Wait States ................4-4 4.4.3 F-Bus Operation .......................4-5 4.4.3.1 Writing the PCB Relocation Register ...............4-6 4.4.3.2...
  • Page 7 CONTENTS PROGRAMMING ......................6-5 6.4.1 Initialization Sequence ....................6-6 6.4.2 Start Address ......................6-10 6.4.3 Stop Address ......................6-10 6.4.4 Enabling and Disabling Chip-Selects ..............6-11 6.4.5 Bus Wait State and Ready Control .................6-11 6.4.6 Overlapping Chip-Selects ..................6-12 6.4.7 Memory or I/O Bus Cycle Decoding ................6-14 6.4.8 Programming Considerations ..................6-14 CHIP-SELECTS AND BUS HOLD................
  • Page 8 CONTENTS 8.3.3.1 Default (Fixed) Priority ...................8-11 8.3.3.2 Changing the Default Priority: Specific Rotation ..........8-11 8.3.3.3 Changing the Default Priority: Automatic Rotation ........8-12 8.3.4 The In-Service Register ..................8-12 8.3.4.1 Clearing the In-Service Bits: Non-Specific End-Of-Interrupt ......8-13 8.3.4.2 Clearing the In-Service Bits: Specific End-Of-Interrupt .........8-13 8.3.4.3 Automatic End-Of-Interrupt Mode ..............8-13 8.3.5...
  • Page 9 CONTENTS CHAPTER 9 TIMER/COUNTER UNIT FUNCTIONAL OVERVIEW.................... 9-1 PROGRAMMING THE TIMER/COUNTER UNIT ............9-6 9.2.1 Initialization Sequence ....................9-11 9.2.2 Clock Sources ......................9-12 9.2.3 Counting Modes ......................9-12 9.2.3.1 Retriggering ....................9-13 9.2.4 Pulsed and Variable Duty Cycle Output ..............9-14 9.2.5 Enabling/Disabling Counters ...................9-15 9.2.6 Timer Interrupts .......................9-16 9.2.7...
  • Page 10 CONTENTS 10.1.11 DMA Module Integration ..................10-12 10.1.11.1 DMA Unit Structure ..................10-13 10.2 PROGRAMMING THE DMA UNIT ................10-15 10.2.1 DMA Channel Parameters ..................10-15 10.2.1.1 Programming the Source and Destination Pointers ........10-15 10.2.1.2 Selecting Byte or Word Size Transfers ............10-19 10.2.1.3 Selecting the Source of DMA Requests ............10-22 10.2.1.4 Arming the DMA Channel ................10-23...
  • Page 11 CONTENTS 11.4 SERIAL COMMUNICATIONS UNIT INTERRUPTS ..........11-21 11.5 SERIAL PORT EXAMPLES..................11-21 11.5.1 Asynchronous Mode Example ................11-21 11.5.2 Mode 0 Example ....................11-23 11.5.3 Master/Slave Example ..................11-24 CHAPTER 12 WATCHDOG TIMER UNIT 12.1 FUNCTIONAL OVERVIEW..................12-1 12.2 USING THE WATCHDOG TIMER AS A SYSTEM WATCHDOG ....... 12-1 12.2.1 Reloading the Watchdog Timer Down Counter ............12-3 12.2.2...
  • Page 12 CONTENTS 14.3.1.2 Arithmetic Instructions ...................14-3 14.3.1.3 Comparison Instructions ................14-5 14.3.1.4 Transcendental Instructions ................14-5 14.3.1.5 Constant Instructions ..................14-6 14.3.1.6 Processor Control Instructions ..............14-6 14.3.2 80C187 Data Types ....................14-7 14.4 MICROPROCESSOR AND COPROCESSOR OPERATION........14-7 14.4.1 Clocking the 80C187 .....................14-10 14.4.2 Processor Bus Cycles Accessing the 80C187 ............14-10 14.4.3 System Design Tips ....................14-11 14.4.4...
  • Page 13 CONTENTS FIGURES Figure Page Simplified Functional Block Diagram of the 80C186 Family CPU ........2-2 Physical Address Generation ..................2-3 General Registers ......................2-4 Segment Registers .......................2-6 Processor Status Word ....................2-9 Segment Locations in Physical Memory..............2-10 Currently Addressable Segments................2-11 Logical and Physical Address ..................2-12 Dynamic Code Relocation ..................2-14 2-10 Stack Operation......................2-16...
  • Page 14 CONTENTS FIGURES Figure Page 3-15 Generating a Normally Not-Ready Bus Signal ............3-16 3-16 Generating a Normally Ready Bus Signal ..............3-17 3-17 Normally Not-Ready System Timing ................3-18 3-18 Normally Ready System Timings ................3-19 3-19 Typical Read Bus Cycle .....................3-22 3-20 Read-Only Device Interface ..................3-23 3-21 Typical Write Bus Cycle....................3-24 3-22...
  • Page 15 CONTENTS FIGURES Figure Page STOP Register Definition .....................6-8 Wait State and Ready Control Functions ..............6-12 Overlapping Chip-Selects...................6-13 Using Chip-Selects During HOLD ................6-15 6-10 Typical System ......................6-16 6-11 Guarded Memory Detector ..................6-20 Refresh Control Unit Block Diagram................7-1 Refresh Control Unit Operation Flow Chart..............7-3 Refresh Address Formation..................7-4 Suggested DRAM Control Signal Timing Relationships..........7-6 Formula for Calculating Refresh Interval for RFTIME Register ........7-7...
  • Page 16 CONTENTS FIGURES Figure Page 8-29 Typical Cascade Connection for 82C59A-2 ...............8-45 8-30 Software Wait State for External 82C59A-2 ...............8-46 Timer/Counter Unit Block Diagram................9-2 Counter Element Multiplexing and Timer Input Synchronization........9-3 Timers 0 and 1 Flow Chart ...................9-4 Timer/Counter Unit Output Modes................9-6 Timer 0 and Timer 1 Control Registers ................9-7 Timer 2 Control Register ....................9-9 Timer Count Registers....................9-10...
  • Page 17 CONTENTS FIGURES Figure Page 11-18 Master/Slave Example .....................11-25 12-1 Block Diagram of the Watchdog Timer Unit ...............12-2 12-2 Watchdog Timer Reset Circuit..................12-2 12-3 Generating Interrupts with the Watchdog Timer............12-3 12-4 WDTOUT Waveforms....................12-6 12-5 WDT Reload Value (High) ..................12-9 12-6 WDT Reload Value (Low)..................12-10 12-7 WDT Count Value (High)..................12-11 12-8...
  • Page 18 CONTENTS TABLES Table Page Comparison of 80C186 Modular Core Family Products ..........1-2 Related Documents and Software................1-3 Implicit Use of General Registers .................2-5 Logical Address Sources....................2-13 Data Transfer Instructions ..................2-18 Arithmetic Instructions ....................2-20 Arithmetic Interpretation of 8-Bit Numbers ..............2-21 Bit Manipulation Instructions ..................2-21 String Instructions.......................2-22 String Instruction Register and Flag Use..............2-23 Program Transfer Instructions ..................2-25...
  • Page 19 CONTENTS TABLES Table Page Instruction Format Variables..................C-1 Instruction Operands ....................C-2 Flag Bit Functions......................C-3 Instruction Set ......................C-4 Operand Variables ...................... D-1 Instruction Set Summary ..................... D-2 Machine Instruction Decoding Guide................D-9 Mnemonic Encoding Matrix ..................D-20 Abbreviations for Mnemonic Encoding Matrix ............D-22 xviii...
  • Page 20 CONTENTS EXAMPLES Example Page Initializing the Power Management Unit for Idle or Powerdown Mode .......5-16 Initializing the Power Management Unit for Power-Save Mode .........5-23 Initializing the Chip-Select Unit...................6-17 Initializing the Refresh Control Unit ................7-12 Initializing the Interrupt Control Unit ................8-47 Template for a Simple Interrupt Handler ..............8-50 Using the Poll Command....................8-51 Configuring a Real-Time Clock...................9-18...
  • Page 22 Introduction...
  • Page 24 As technology advanced and turned toward small geometry CMOS processes, it became clear that a new 80186 was needed. In 1987 Intel announced the second generation of the 80186 family: the 80C186/C188. The 80C186 family is pin compatible with the 80186 family, while adding an enhanced feature set.
  • Page 25: Introduction

    INTRODUCTION The 80C186 Modular Core family is the direct result of ten years of Intel development. It offers the designer the peace of mind of a well-established architecture with the benefits of state-of-the- art technology. Table 1-1. Comparison of 80C186 Modular Core Family Products...
  • Page 26: Related Documents

    The following table lists documents and software that are useful in designing systems that incor- porate the 80C186 Modular Core Family. These documents are available through Intel Literature. In the U.S. and Canada, call 1-800-548-4725 to order. In Europe and other international locations, please contact your local Intel sales office or distributor.
  • Page 27: Electronic Support Systems

    Available on BBS ELECTRONIC SUPPORT SYSTEMS Intel’s FaxBack* service and application BBS provide up-to-date technical information. Intel also maintains several forums on CompuServe and offers a variety of information on the World Wide Web. These systems are available 24 hours a day, 7 days a week, providing technical infor- mation whenever you need it.
  • Page 28: Bulletin Board System (Bbs)

    BBS file listings Microprocessor, PCI, and peripheral catalog Quality and reliability and change notification catalog iAL (Intel Architecture Labs) technology catalog 1.3.2 Bulletin Board System (BBS) The bulletin board system (BBS) lets you download files to your computer. The application BBS has the latest ApBUILDER software, hypertext manuals and datasheets, software drivers, firm- ware upgrades, application notes and utilities, and quality and reliability data.
  • Page 29: How To Find Ap Builder Software And Hypertext Documents On The Bbs

    BBS. To access the files, complete these steps: Type F from the BBS Main menu. The BBS displays the Intel Apps Files menu. Type L and press <Enter>. The BBS displays the list of areas and prompts for the area number.
  • Page 30: Product Literature

    44(0)1793-431155 Europe (U.K.) 44(0)1793-421333 Germany 44(0)1793-421777 France 81(0)120-47-88-32 Japan (fax only) TRAINING CLASSES In the U.S. and Canada, you can register for training classes through the Intel customer training center. Classes are held in the U.S. 1-800-234-8806 U.S. and Canada...
  • Page 32: Overview Of The 80C186 Family Architecture

    Overview of the 80C186 Family Architecture...
  • Page 34: Architectural Overview

    CHAPTER 2 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The 80C186 Modular Microprocessor Core shares a common base architecture with the 8086, 8088, 80186, 80188, 80286, Intel386™ and Intel486™ processors. The 80C186 Modular Core maintains full object-code compatibility with the 8086/8088 family of 16-bit microprocessors, while adding hardware and software performance enhancements.
  • Page 35: Execution Unit

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Address Bus (20 Bits) General Σ Registers Data (16 Bits) ALU Data Bus Internal Communications (16 Bits) Registers Temporary Registers External Control Logic Instruction Queue Control 1 2 3 4 5 6 System Q Bus Flags (8 Bits) Execution Unit...
  • Page 36: Bus Interface Unit

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The Execution Unit does not connect directly to the system bus. It obtains instructions from a queue maintained by the Bus Interface Unit. When an instruction requires access to memory or a peripheral device, the Execution Unit requests the Bus Interface Unit to read and write data. Ad- dresses manipulated by the Execution Unit are 16 bits wide.
  • Page 37: General Registers

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE During periods when the Execution Unit is busy executing instructions, the Bus Interface Unit sequentially prefetches instructions from memory. As long as the prefetch queue is partially full, the Execution Unit fetches instructions. 2.1.3 General Registers The 80C186 Modular Core family CPU has eight 16-bit general registers (see Figure 2-3).
  • Page 38: Segment Registers

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The data registers can be addressed by their upper or lower halves. Each data register can be used interchangeably as a 16-bit register or two 8-bit registers. The pointer registers are always access- ed as 16-bit values. The CPU can use data registers without constraint in most arithmetic and log- ic operations.
  • Page 39: Instruction Pointer

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Code Segment Data Segment Stack Segment Extra Segment Figure 2-4. Segment Registers 2.1.5 Instruction Pointer The Bus Interface Unit updates the 16-bit Instruction Pointer (IP) register so it contains the offset of the next instruction to be fetched. Programs do not have direct access to the Instruction Pointer, but it can change, be saved or be restored as a result of program execution.
  • Page 40: Flags

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.6 Flags The 80C186 Modular Core family has six status flags (see Figure 2-5) that the Execution Unit posts as the result of arithmetic or logical operations. Program branch instructions allow a pro- gram to alter its execution depending on conditions flagged by a prior operation. Different in- structions affect the status flags differently, generally reflecting the following states: •...
  • Page 41: Memory Segmentation

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.7 Memory Segmentation Programs for the 80C186 Modular Core family view the 1 Mbyte memory space as a group of user-defined segments. A segment is a logical unit of memory that can be up to 64 Kbytes long. Each segment is composed of contiguous memory locations.
  • Page 42: Processor Status Word

    NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 2-5. Processor Status Word...
  • Page 43: Logical Addresses

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Fully Overlapped Partly Segment D Disjoint Overlapped Logical Contiguous Segment C Segments Segment E Segment A Segment B Physical Memory 10000H 20000H 30000H A1036-0A Figure 2-6. Segment Locations in Physical Memory The four segment registers point to four “currently addressable” segments (see Figure 2-7). The currently addressable segments provide a work space consisting of 64 Kbytes for code, a 64 Kbytes for stack and 128 Kbytes for data storage.
  • Page 44 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE FFFFFH Data: Code: Stack: Extra: A1037-0A Figure 2-7. Currently Addressable Segments The segment register is automatically selected according to the rules in Table 2-2. All information in one segment type generally shares the same logical attributes (e.g., code or data). This leads to programs that are shorter, faster and better structured.
  • Page 45 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2C4H Physical 2C3H Address 2C2H Offset (3H) 2C1H Segment 2C0H Base 2BFH 2BEH 2BDH 2BCH 2BBH Offset Logical 2BAH (13H) Addresses 2B9H 2B8H 2B7H 2B6H 2B5H 2B4H 2B3H 2B2H 2B1H Segment 2B0H Base A1038-0A Figure 2-8.
  • Page 46: Dynamically Relocatable Code

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-2. Logical Address Sources Default Alternate Type of Memory Reference Offset Segment Base Segment Base Instruction Fetch NONE Stack Operation NONE Variable (except following) CS, ES, SS Effective Address String Source CS, ES, SS String Destination NONE BP Used as Base Register...
  • Page 47 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Before After Relocation Relocation Code Segment Stack Segment Code Segment Data Stack Segment Segment Data Segment Extra Extra Segment Segment Free Space A1039-0A Figure 2-9. Dynamic Code Relocation To be dynamically relocatable, a program must not load or alter its segment registers and must not transfer directly to a location outside the current code segment.
  • Page 48: 2.1.10 Stack Implementation

    0FFFF0H. • Locations 0F8H through 0FFH in I/O space are reserved for communication with other Intel hardware products and must not be used. On the 80C186 core, these addresses are used as I/O ports for the 80C187 numerics processor extension.
  • Page 49 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE POP AX POP BX PUSH AX Existing Stack 1062 1062 1062 1060 1060 1060 105E 105E 105E 105B 105B 105B 105A 105A 105A 1058 1058 1058 1056 1056 1056 1054 1054 1054 1052 1052 1052 1050 1050...
  • Page 50: Software Overview

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE SOFTWARE OVERVIEW All 80C186 Modular Core family members execute the same instructions. This includes all the 8086/8088 instructions plus several additions and enhancements (see Appendix A, “80C186 In- struction Set Additions and Extensions”). The following sections describe the instructions by cat- egory and provide a detailed discussion of the operand addressing modes.
  • Page 51: Data Transfer Instructions

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.1 Data Transfer Instructions The instruction set contains 14 data transfer instructions. These instructions move single bytes and words between memory and registers. They also move single bytes and words between the AL or AX register and I/O ports. Table 2-3 lists the four types of data transfer instructions and their functions.
  • Page 52: Arithmetic Instructions

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE LAHF Z U A U P U C SAHF 6 5 4 3 2 1 0 PUSHF POPF U = Undefined; Value is indeterminate O = Overflow Flag D = Direction Flag I = Interrupt Enable Flag T = Trap Flag S = Sign Flag Z = Zero Flag...
  • Page 53 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-5 shows the interpretations of various bit patterns according to number type. Binary num- bers can be 8 or 16 bits long. Decimal numbers are stored in bytes, two digits per byte for packed decimal and one digit per byte for unpacked decimal.
  • Page 54: Bit Manipulation Instructions

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-5. Arithmetic Interpretation of 8-Bit Numbers Unsigned Signed Unpacked Packed Bit Pattern Binary Binary Decimal Decimal 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 –119 invalid 1 1 0 0 0 1 0 1 –59...
  • Page 55: String Instructions

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Individual bits in bytes and words can also be rotated. The processor does not discard the bits ro- tated out of an operand. The bits circle back to the other end of the operand. The number of bits to be rotated is taken from the count operand, which can specify either an immediate value or the CL register.
  • Page 56: Program Transfer Instructions

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE String instructions automatically update the SI register, the DI register, or both, before processing the next string element. The Direction Flag (DF) determines whether the index registers are auto- incremented (DF = 0) or auto-decremented (DF = 1). The processor adjusts the DI, SI, or both registers by one for byte strings or by two for word strings.
  • Page 57 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Unconditional transfer instructions can transfer control either to a target instruction within the current code segment (intrasegment transfer) or to a different code segment (intersegment trans- fer). The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans- fer FAR.
  • Page 58 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-9. Program Transfer Instructions Conditional Transfers JA/JNBE Jump if above/not below nor equal JAE/JNB Jump if above or equal/not below JB/JNAE Jump if below/not above nor equal JBE/JNA Jump if below or equal/not above Jump if carry JE/JZ Jump if equal/zero...
  • Page 59 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Iteration control instructions can be used to regulate the repetition of software loops. These in- structions use the CX register as a counter. Like the conditional transfers, the iteration control in- structions are self-relative and can transfer only to targets that are within –128 to +127 bytes of themselves.
  • Page 60: Processor Control Instructions

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.6 Processor Control Instructions Processor control instructions (see Table 2-11) allow programs to control various CPU functions. Seven of these instructions update flags, four of them are used to synchronize the microprocessor with external events, and the remaining instruction causes the CPU to do nothing. Except for flag operations, processor control instructions do not affect the flags.
  • Page 61: Memory Addressing Modes

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Immediate operands are constant data contained in an instruction. Immediate data can be either 8 or 16 bits in length. Immediate operands are available directly from the instruction queue and can be accessed quickly. As with a register operand, no bus cycles need to be run to get an imme- diate operand.
  • Page 62 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Single Index Double Index Encoded in the Instruction Explicit Effective in the Displacement Address Instruction 0000 0000 Assumed Unless Overridden by Prefix 0000 0000 Physical Addr A1015-0A Figure 2-12. Memory Address Computation The displacement is an 8- or 16-bit number contained in the instruction. The displacement gen- erally is derived from the position of the operand’s name (a variable or label) in the program.
  • Page 63 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The BX or BP register can be specified as the base register for an effective address calculation. Similarly, either the SI or the DI register can be specified as the index register. The displacement value is a constant.
  • Page 64 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Opcode Mod R/M A1017-0A Figure 2-14. Register Indirect Addressing Opcode Mod R/M Displacement A1018-0A Figure 2-15. Based Addressing Based addressing provides a simple way to address data structures that may be located in different places in memory (see Figure 2-16).
  • Page 65 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE High Address Displacement Displacement (Rate) Status (Rate) Rate Sick Base Base Register Register Dept Employee Status Rate Sick Dept Employee Low Address A1019-0A Figure 2-16. Accessing a Structure with Based Addressing With indexed addressing, the effective address is calculated by summing a displacement and the contents of an index register (SI or DI, see Figure 2-17).
  • Page 66 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Opcode Mod R/M Displacement A1020-0A Figure 2-17. Indexed Addressing High Address Array (8) Displacement Array (7) Displacement Array (6) Array (5) Index Register Index Register Array (4) Array (3) Array (2) Array (1) Array (0) 1 Word Low Address A1021-0A...
  • Page 67 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Based index addressing generates an effective address that is the sum of a base register, an index register and a displacement (see Figure 2-19). The two address components can be determined at execution time, making this a very flexible addressing mode. Opcode Mod R/M Displacement...
  • Page 68 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE High Address Displacement Parm 2 Displacement Parm 1 Old BP Base Register (BP) Base Register (BP) Old BX Old AX Array (6) Index Register Index Register Array (5) Array (4) Array (3) Array (2) Array (1) Array (0) Count...
  • Page 69: I/O Port Addressing

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Opcode Source EA Destination EA A1025-0A Figure 2-21. String Operand 2.2.2.3 I/O Port Addressing Any memory operand addressing modes can be used to access an I/O port if the port is memory- mapped. String instructions can also be used to transfer data to memory-mapped ports with an appropriate hardware interface.
  • Page 70: Data Types Used In The 80C186 Modular Core Family

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.2.4 Data Types Used in the 80C186 Modular Core Family The 80C186 Modular Core family supports the data types described in Table 2-12 and illustrated in Figure 2-23. In general, individual data elements must fit within defined segment limits. Table 2-12.
  • Page 71 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Signed Byte Unsigned Byte Sign Bit Magnitude Magnitude 15 14 Unsigned Signed Word Word Sign Bit Magnitude Magnitude Signed Double Word* Sign Bit Magnitude Signed Quad Word* Sign Bit Magnitude Binary Coded Decimal (BCD) BCD Digit n BCD Digit 1 BCD Digit 0...
  • Page 72: Interrupts And Exception Handling

    Each interrupt or exception is given a type number, 0 through 255, corresponding to its position in the Interrupt Vector Table. Note that in- terrupt types 0–31 are reserved for Intel and should not be used by an application program. 2-39...
  • Page 73 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Memory Table Vector Memory Table Vector Address Entry Definition Address Entry Definition Type 7 - Esc Type 255 Opcode User Type 6 - Unused Available Opcode Type 32 Type 5 - Array Bounds Type 31 Type 4 - Overflow Reserved Type 3 - Breakpoint...
  • Page 74 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The CPU is now executing the interrupt service routine. The programmer must save (usually by pushing onto the stack) all registers used in the interrupt service routine; otherwise, their contents will be lost. To allow nesting of maskable interrupts, the programmer must set the Interrupt En- able bit in the Processor Status Word.
  • Page 75: Non-Maskable Interrupts

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.3.1.1 Non-Maskable Interrupts The Non-Maskable Interrupt (NMI) is the highest priority interrupt. It is usually reserved for a catastrophic event such as impending power failure. An NMI cannot be prevented (or masked) by software. When the NMI input is asserted, the interrupt processing sequence begins after ex- ecution of the current instruction completes (see “Interrupt Latency”...
  • Page 76 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Single Step — Type 1 The Single Step trap occurs after the CPU executes one instruction with the Trap Flag (TF) bit set in the Processor Status Word. This allows programs to execute one instruction at a time. Inter- rupts are not generated after prefix instructions (e.g., REP), after instructions that modify segment registers (e.g., POP DS) or after the WAIT instruction.
  • Page 77: Software Interrupts

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Numerics Coprocessor Fault — Type 16 The Numerics Coprocessor fault is caused by an external 80C187 numerics coprocessor. The 80C187 reports the exception by asserting the ERROR pin. The 80C186 Modular Core checks the ERROR pin only when executing a numerics instruction. A Numerics Coprocessor Fault in- dicates that the previous numerics instruction caused the exception.
  • Page 78: Interrupt Response Time

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The CPU can recognize interrupts only on valid instruction boundaries. A valid instruction boundary usually occurs when the current instruction finishes. The following is a list of excep- tions: MOVs and POPs referencing a segment register delay the servicing of interrupts until after the following instruction.
  • Page 79: Interrupt And Exception Priority

    OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Clocks Idle Read IP Idle Read CS Idle Push Flags Idle Push CS Push IP Idle First Instruction Fetch From Interrupt Routine Total 42 A1030-0A Figure 2-27. Interrupt Response Factors 2.3.5 Interrupt and Exception Priority Interrupts can be recognized only on valid instruction boundaries.
  • Page 80 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE F = 1 Divide Divide Error Push PSW, CS, IP Fetch Divide Error Vector Push PSW, CS, IP Fetch NMI Vector Execute NMI Service Routine IRET Execute Divide Service Routine IRET A1031-0A Figure 2-28. Simultaneous NMI and Exception Single step priority is a special case.
  • Page 81 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE To prevent the single-step routine from executing before a maskable interrupt, disable interrupts while single stepping an instruction, then enable interrupts in the single step service routine. The maskable interrupt is serviced from within the single step service routine and that interrupt ser- vice routine is not single-stepped.
  • Page 82 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Interrupt Enable Bit (IE) = 1 Trap Flag (TF) = 1 Divide Timer Interrupt Push PSW, CS, IP Interrupt Enable Bit (IE) = 0 Fetch Divide Error Vector Trap Flag (TF) = 0 Interrupt Enable Bit (IE) = 0 Push PSW, CS, IP Trap Flag (TF) = 0 Fetch NMI Vector...
  • Page 84 Bus Interface Unit...
  • Page 86: Address And Data Bus Concepts

    CHAPTER 3 BUS INTERFACE UNIT The Bus Interface Unit (BIU) generates bus cycles that prefetch instructions from memory, pass data to and from the execution unit, and pass data to and from the integrated peripheral units. The BIU drives address, data, status and control information to define a bus cycle. The start of a bus cycle presents the address of a memory or I/O location and status information defining the type of bus cycle.
  • Page 87 BUS INTERFACE UNIT Physical Implementation Physical Implementation of the Address Space for of the Address Space for 16-Bit Systems 8-Bit Systems 1 MByte 512 KBytes 512 KBytes FFFFF FFFFF FFFFE FFFFE FFFFD FFFFC A19:0 D7:0 A19:1 D15:8 D7:0 A1100-0A Figure 3-1. Physical Data Bus Models Byte transfers to even addresses transfer information over the lower half of the data bus (see Fig- ure 3-2).
  • Page 88 BUS INTERFACE UNIT Even Byte Transfer Y + 1 X + 1 A19:1 D15:8 D7:0 (Low) (High) Odd Byte Transfer Y + 1 (X + 1) A19:1 D7:0 D15:8 (High) (Low) A1104-0A Figure 3-2. 16-Bit Data Bus Byte Transfers...
  • Page 89 BUS INTERFACE UNIT (X + 1) A19:1 D15:8 D7:0 (Low) (Low) A1107-0A Figure 3-3. 16-Bit Data Bus Even Word Transfers During a byte read operation, the BIU floats the entire 16-bit data bus, even though the transfer occurs on only one half of the bus. This action simplifies the decoding requirements for read-only devices (e.g., ROM, EPROM, Flash).
  • Page 90: Bit Data Bus

    BUS INTERFACE UNIT First Bus Cycle (X + 1) A19:1 D15:8 D7:0 (High) (Low) Second Bus Cycle Y + 1 X + 1 A19:1 D15:8 D7:0 (Low) (High) A1108-0A Figure 3-4. 16-Bit Data Bus Odd Word Transfers 3.2.2 8-Bit Data Bus The memory address space on an 8-bit data bus is physically implemented as one bank of 1 Mbyte (see Figure 3-1 on page 3-2).
  • Page 91: Memory And I/O Interfaces

    BUS INTERFACE UNIT For word transfers, the word address defines the first byte transferred. The second byte transfer occurs from the word address plus one. Figure 3-5 illustrates a word transfer on an 8-bit bus in- terface. Second Bus Cycle First Bus Cycle (X + 1) A19:0...
  • Page 92: Bit Bus Memory And I/O Requirements

    BUS INTERFACE UNIT 3.3.1 16-Bit Bus Memory and I/O Requirements A 16-bit bus has certain assumptions that must be met to operate properly. Memory used to store instruction operands (i.e., the program) and immediate data must be 16 bits wide. Instruction prefetch bus cycles require that both banks be used.
  • Page 93 BUS INTERFACE UNIT CLKOUT Valid Status S2:0 Data AD15:0 Address RD / WR A1507-0A Figure 3-6. Typical Bus Cycle Falling Rising CLKOUT Edge Edge Phase 1 Phase 2 (High Phase) (Low Phase) A1111-0A Figure 3-7. T-State Relation to CLKOUT Figure 3-8 shows the BIU state diagram. Typically a bus cycle consists of four consecutive T- states labeled T1, T2, T3 and T4.
  • Page 94 BUS INTERFACE UNIT The address/status phase starts just before T1 and continues through T1. The data phase starts at T2 and continues through T4. Figure 3-9 illustrates the T-state relationship of the two phases. Bus Ready Request Pending HOLD Deasserted Halt Bus Cycle Bus Not Ready...
  • Page 95: Address/Status Phase

    BUS INTERFACE UNIT or TI or TW or TI CLKOUT Address/ Data Phase Status Phase A1113-0A Figure 3-9. T-State and Bus Phases 3.4.1 Address/Status Phase Figure 3-10 shows signal timing relationships for the address/status phase of a bus cycle. A bus cycle begins with the transition of ALE and S2:0.
  • Page 96 BUS INTERFACE UNIT or TI CLKOUT AD15:0 A19:16 Valid S2:0 Valid NOTES: : Clock high to ALE high, S2:0 valid. CHOV : Clock low to address valid, BHE valid. CLOV : Address valid to ALE low (address setup to ALE). AVLL : Clock high to ALE low.
  • Page 97 BUS INTERFACE UNIT Latched Address Signals Signals From CPU A19:16 LA19:16 S2:0 LS2:0 AD15:8 LA15:8 AD7:0 LA7:0 A1102-0A Figure 3-11. Demultiplexing Address Information Table 3-1. Bus Cycle Types Status Bit Operation Interrupt Acknowledge I/O Read I/O Write Halt Instruction Prefetch Memory Read Memory Write Idle (passive)
  • Page 98: Data Phase

    BUS INTERFACE UNIT 3.4.2 Data Phase Figure 3-12 shows the timing relationships for the data phase of a bus cycle. The only bus cycle type that does not have a data phase is a bus halt. During the data phase, the bus transfers infor- mation between the internal units and the memory or peripheral device selected during the ad- dress/status phase.
  • Page 99 BUS INTERFACE UNIT or TW or TI CLKOUT RD/ WR AD15:0 Valid Write Data Write Valid AD15:0 Read Data Read S2:0 NOTES: : Clock low to valid RD/ WR active; Write data valid CLOV : Clock low to status inactive CLOV : Data input valid to clock low CLIS...
  • Page 100 BUS INTERFACE UNIT CLKOUT Valid S2:0 Address A19:16 Address Valid Write Data AD15:0 READY A1040-0A Figure 3-13. Typical Bus Cycle with Wait States READY BUS READY Rising Falling CLKOUT Edge Edge A1079-01 Figure 3-14. READY Pin Block Diagram 3-15...
  • Page 101 BUS INTERFACE UNIT A normally not-ready system is one in which READY remains low at all times except to signal a ready condition. For any bus cycle, only the selected device drives the READY input high to complete the bus cycle. The circuit shown in Figure 3-15 illustrates a simple circuit to generate a normally not-ready signal.
  • Page 102 BUS INTERFACE UNIT Wait State Module Enable READY Load CLKOUT Clock A1081-0A Figure 3-16. Generating a Normally Ready Bus Signal The READY input has two major timing concerns that can affect whether a normally ready or normally not-ready signal may be required. Two latches capture the state of the READY input (see Figure 3-14 on page 3-15).
  • Page 103: Idle States

    BUS INTERFACE UNIT or T3 or TW or TW or TW CLKOUT READY In a Normally-Not-Ready system, wait states will be inserted until both 1 & 2 are met. : READY active to clock high (assumes Ready remains CHIS active between 1 & 2) : READY hold from clock low CLIH A1082-0A...
  • Page 104 BUS INTERFACE UNIT CLKOUT READY In a Normally-Ready system, a wait state will be inserted when 1 & 2 are met. : READY low to clock high CHIS : READY hold from clock high CHIH CLKOUT READY Alternatively, in a Normally-Ready system, a wait state will be inserted when1 & 2 are met. : READY low to clock low CLIS : READY hold from clock low...
  • Page 105: Bus Cycles

    BUS INTERFACE UNIT An idle bus state may or may not drive the bus. An idle bus state following a bus read cycle con- tinues to float the bus. An idle bus state following a bus write cycle continues to drive the bus. The BIU drives no control strobes active in an idle state except to indicate the start of another bus cycle.
  • Page 106 BUS INTERFACE UNIT Figure 3-20 illustrates a typical 16-bit interface connection to a read-only device interface. The same example applies to an 8-bit bus system, except that no devices connect to an upper bus. Four parameters (Table 3-3) must be evaluated when determining the compatibility of a memory (or I/O) device.
  • Page 107: Refresh Bus Cycles

    BUS INTERFACE UNIT CLKOUT Status Valid S2:0 Address Valid A18:16 = 0, A19=Valid Status A19:16 A15:8 Valid RFSH A15:0 Data Address [AD7:0] Valid Valid DT / R A1084-0A Figure 3-19. Typical Read Bus Cycle 3.5.1.1 Refresh Bus Cycles A refresh bus cycle operates similarly to a normal read bus cycle except for the following: •...
  • Page 108: Write Bus Cycles

    BUS INTERFACE UNIT AD7:0 O 0-7 27C256 LA15:1 A 0-14 A 0-14 27C256 AD15:8 O 0-7 Note: A and BHE are not used. A1105-0A Figure 3-20. Read-Only Device Interface 3.5.2 Write Bus Cycles Figure 3-21 illustrates a typical write bus cycle. The bus cycle starts with the transition of ALE high and the generation of valid status bits S2:0.
  • Page 109 BUS INTERFACE UNIT CLKOUT Status Valid S2:0 Address Valid A18:16 = 0, A19=Valid Status A19:16 Valid [A15:8] AD15:0 Address Data Valid Valid [AD7:0] DT/R A1085-0A Figure 3-21. Typical Write Bus Cycle Table 3-4. Write Bus Cycle Types Status Bits Bus Cycle Type Write I/O —...
  • Page 110 BUS INTERFACE UNIT Most memory and peripheral devices latch data on the rising edge of the write strobe. Address, chip-select and data must be valid (set up) prior to the rising edge of WR. T and T fine the minimum data setup requirements. The value calculated by their respective equations must be greater than the device requirements.
  • Page 111: Interrupt Acknowledge Bus Cycle

    BUS INTERFACE UNIT The minimum device data hold time (from WR high) is defined by T . The calculated value must be greater than the minimum device requirements; however, the value can be changed only by decreasing the clock rate. Table 3-5.
  • Page 112 BUS INTERFACE UNIT CLKOUT S2:0 INTA AD15:13 CAS (Slave ID) Valid [A15:13] AD12:0 Note [AD7:0] LOCK DT / R A19:16 A12:8 are unknown [A12:8] A19:16 are driven low RD, WR NOTE: Vector Type is read from AD7:0 only. Figure 3-23. Interrupt Acknowledge Bus Cycle 3-27...
  • Page 113: System Design Considerations

    BUS INTERFACE UNIT Figure 3-24 shows a typical 82C59A interface example. Bus ready must be provided to terminate both bus cycles in the interrupt acknowledge sequence. NOTE Due to an internal condition, external ready is ignored if the device is configured in Cascade mode and the Peripheral Control Block (PCB) is located at 0000H in I/O space.
  • Page 114: Halt Bus Cycle

    BUS INTERFACE UNIT 3.5.4 HALT Bus Cycle Suspending the CPU reduces device power consumption and potentially reduces interrupt latency time. The HLT instruction initiates two events: Suspends the Execution Unit. Instructs the BIU to execute a HALT bus cycle. The Idle or Powerdown power management mode (or the absence of both of them, known as Ac- tive Mode) affects the operation of the bus HALT cycle.
  • Page 115 BUS INTERFACE UNIT After several TI bus states, all address/data, address/status and bus control pins drive to a known state when Powerdown or Idle Mode is enabled. The address/data and address/status bus pins force a low (0) state. Bus control pins force their inactive state. Figure 3-3 lists the state of each pin after entering the HALT bus state.
  • Page 116 BUS INTERFACE UNIT CLKOUT S2:0 AD15:0 Note 1 Note 2 Note 3 [AD7:0] [A15:8] Note 2 Note 2 Note 3 A19:16 Note 4 [RFSH = 1] NOTES: 1. The AD15:0 [AD7:0] bus can be floating, driving a previous write data value, or driving the next instruction prefetch address value.
  • Page 117: Temporarily Exiting The Halt Bus State

    BUS INTERFACE UNIT 3.5.5 Temporarily Exiting the HALT Bus State A DMA request, refresh request or bus hold request causes the BIU to exit the HALT bus state temporarily. This can occur only when in the Active or Idle power management mode. The BIU returns to the HALT bus state after it completes the desired bus operation.
  • Page 118 BUS INTERFACE UNIT CLKOUT S2:0 AD15:0 Addr [AD7:0] [A15:8] Address Note 1 A19:16 Note 1 Addr A19 = 1, A18:16 = 0 Note 2 Note 3 RFSH NOTE: 1. Previous bus cycle value. 2. Only occurs for BHE on the first refresh bus cycle after entering HALT. 3.
  • Page 119: Exiting Halt

    BUS INTERFACE UNIT T1 T2 T3 T4 T1 T2 T3 CLKOUT S2:0 Valid Status Valid Status AD15:0 Valid Data Addr Addr [AD7:0] [A15:8] Note Address Address A19:16 Addr Note Addr Note Valid Valid [RFSH=1] NOTE: Drives previous bus cycle value A1090-0A Figure 3-28.
  • Page 120 BUS INTERFACE UNIT CLKOUT 8 1/2 clocks to first vector fetch S2:0 AD15:0 [AD7:0] [A15:8] Note [RFSH = 1] A19:16 Time is determined by PDTMR (4 1/2 clocks min.) NMI, INTx NOTE: Previous bus cycle address value. A1092-0A Figure 3-29. Exiting HALT (Powerdown Mode) 3-35...
  • Page 121: System Design Alternatives

    BUS INTERFACE UNIT CLKOUT Note 1 NMI/NTx S2:0 Valid AD15:0 Note 2 Addr [AD7:0] [A15:8] Address Note 3 A19:16 Note 4 Note 3 RFSH NOTE: 1. For NMI, delay = 4 1/2 clocks. For INTx, delay = 7 1/2 clocks (min). 2.
  • Page 122: Buffering The Data Bus

    BUS INTERFACE UNIT 3.6.1 Buffering the Data Bus The BIU generates two control signals, DEN and DT/R, to control bidirectional buffers or trans- ceivers. The timing relationship of DEN and DT/R is shown in Figure 3-31. The following con- ditions require transceivers: •...
  • Page 123 BUS INTERFACE UNIT A19:16 Latch Address Bus Processor AD15:0 Address Memory Transceiver Data Data Bus Device DT/ R CPU Local Bus Buffered Bus A1095-0A Figure 3-32. Buffered AD Bus System In a fully buffered system, DEN directly drives the transceiver output enable. A partially buffered system requires that DEN be qualified with another signal to prevent the transceiver from going active for local bus accesses.
  • Page 124: Synchronizing Software And Hardware Events

    BUS INTERFACE UNIT AD15:8 D15:8 GCS0 Buffer Buffered Data AD7:0 D7:0 DT / R Buffer Local Data A1096-01 Figure 3-33. Qualifying DEN with Chip-Selects 3.6.2 Synchronizing Software and Hardware Events The execution sequence of a program and hardware events occurring within a system are often asynchronous to each other.
  • Page 125: Using A Locked Bus

    BUS INTERFACE UNIT The WAIT instruction suspends program execution until one of two events occurs: an interrupt is generated, or the TEST input pin is sampled low. Unlike interrupts, the TEST input pin does not require that program execution be transferred to a new location (i.e., an interrupt routine is not executed).
  • Page 126: Multi-Master Bus System Designs

    BUS INTERFACE UNIT In general, prefix bytes (such as LOCK) are considered extensions of the instructions they pre- cede. Interrupts, DMA requests and refresh requests that occur during execution of the prefix are not acknowledged until the instruction following the prefix completes (except for instructions that are servicing interrupts during their execution, such as HALT, WAIT and repeated string primitives).
  • Page 127: Hold Bus Latency

    BUS INTERFACE UNIT CLKOUT HOLD HLDA AD15:0 Float A19:16 RD,WR Float DT/R S2:0,BHE LOCK NOTES: : HOLD input to clock low CLIS : Clock high to output float CHOF : Clock low to output float CLOF : Clock low to HLDA high CLOV A1097-0A Figure 3-34.
  • Page 128: Refresh Operation During A Bus Hold

    BUS INTERFACE UNIT The major factors that influence bus latency are listed below (in order from longest delay to short- est delay). Bus Not Ready — As long as the bus remains not ready, a bus hold request cannot be serviced.
  • Page 129 BUS INTERFACE UNIT CLKOUT HOLD HLDA AD15:0 RD, WR, BHE, S2:0 DT / R, A19:16 LOCK NOTES: 1. : HLDA is deasserted, signaling need to run refresh bus cycle 2. : External bus master terminates use of the bus 3. : HOLD deasserted 4.
  • Page 130: Exiting Hold

    BUS INTERFACE UNIT Latched HLDA HLDA RESOUT HOLD A1310-0A Figure 3-36. Latching HLDA The removal of HOLD must be detected for at least one clock cycle to allow the BIU to regain the bus and execute a refresh bus cycle. Should HOLD go active before the refresh bus cycle is complete, the BIU will release the bus and generate HLDA.
  • Page 131: Bus Cycle Priorities

    BUS INTERFACE UNIT CLKOUT HOLD HLDA AD15:0 RD, WR, BHE, DT / R, S2:0, A19:16 NOTES: : HOLD recognition setup to clock low CLIS : HOLD internally synchronized : Clock low to HLDA low CLOV : Clock high to signal active (high or low) CHOV : Clock low to signal active (high or low) CLOV...
  • Page 132 BUS INTERFACE UNIT Internal error (e.g., divide error, overflow) interrupt vectoring sequence. Hardware (e.g., INT0, DMA) interrupt vectoring sequence. 80C187 Math Coprocessor error interrupt vectoring sequence. DMA bus cycles. 10. General instruction execution. This category includes read/write operations following a pipelined effective address calculation, vectoring sequences for software interrupts and numerics code execution.
  • Page 134 Peripheral Control Block...
  • Page 136: Peripheral Control Registers

    CHAPTER 4 PERIPHERAL CONTROL BLOCK All integrated peripherals in the 80C186 Modular Core family are controlled by sets of registers within an integrated Peripheral Control Block (PCB). The peripheral control registers are physi- cally located in the peripheral devices they control, but they are addressed as a single block of registers.
  • Page 137 PCB is mapped to I/O space. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 4-1. PCB Relocation Register Table 4-1. Peripheral Control Block...
  • Page 138 PERIPHERAL CONTROL BLOCK Table 4-1. Peripheral Control Block Function Function Function Function Offset Offset Offset Offset SPICP0 Reserved GCS1ST D0DSTL SPICP1 T2CON GCS1SP D0DSTH Reserved P3DIR GCS2ST D0TC SCUIRL P3PIN GCS2SP D0CON DMAIRL P3CON GCS3ST DMAPRI TIMIRL P3LTCH GCS3SP DMAHALT Reserved P1DIR GCS4ST...
  • Page 139: Reserved Locations

    PERIPHERAL CONTROL BLOCK RESERVED LOCATIONS Many locations within the Peripheral Control Block are not assigned to any peripheral. Unused locations are reserved. Reading from these locations yields an undefined result. If reserved reg- isters are written (for example, during a block MOV instruction) they must be set to 0H. NOTE Failure to follow this guideline could result in incompatibilities with future 80C186 Modular Core family products.
  • Page 140: F-Bus Operation

    PERIPHERAL CONTROL BLOCK 4.4.3 F-Bus Operation The F-Bus functions differently than the external data bus for byte and word accesses. All write transfers on the F-Bus occur as words, regardless of how they are encoded. For example, the in- struction OUT DX, AL (DX is even) will write the entire AX register to the Peripheral Control Block register at location [DX].
  • Page 141: Writing The Pcb Relocation Register

    PERIPHERAL CONTROL BLOCK 4.4.3.1 Writing the PCB Relocation Register Whenever mapping the Peripheral Control Block to another location, the user should program the Relocation Register with a byte write (i.e., OUT DX, AL). Internally, the Relocation Register is written with 16 bits of the AX register, while externally the Bus Interface Unit runs a single 8-bit bus cycle.
  • Page 142: Considerations For The 80C187 Math Coprocessor Interface

    PERIPHERAL CONTROL BLOCK As an example, to relocate the Peripheral Control Block to the memory range 10000-100FFH, the user would program the PCB Relocation Register with the value 1100H. Since the Relocation Register is part of the Peripheral Control Block, it relocates to word 10000H plus its fixed offset. NOTE Due to an internal condition, external ready is ignored if the device is configured in Cascade mode and the Peripheral Control Block (PCB) is...
  • Page 144 Clock Generation and Power Management...
  • Page 146: Crystal Oscillator

    CHAPTER 5 CLOCK GENERATION AND POWER MANAGEMENT The clock generation and distribution circuits provide uniform clock signals for the Execution Unit, the Bus Interface Unit and all integrated peripherals. The 80C186 Modular Core Family processors have additional logic that controls the clock signals to provide power management functions.
  • Page 147: Oscillator Operation

    CLOCK GENERATION AND POWER MANAGEMENT 5.1.1.1 Oscillator Operation A phase shift oscillator operates through positive feedback, where a non-inverted, amplified ver- sion of the input connects back to the input. A 360° phase shift around the loop will sustain the feedback in the oscillator.
  • Page 148 CLOCK GENERATION AND POWER MANAGEMENT Choose C and L component values in the third overtone crystal circuit to satisfy the following conditions: • The LC components form an equivalent series resonant circuit at a frequency below the fundamental frequency. This criterion makes the circuit inductive at the fundamental frequency.
  • Page 149 CLOCK GENERATION AND POWER MANAGEMENT (a) Series or Parallel Resonant Frequency (b) Equivalent Capacitance ω – – ------------------------ - ----------------------------------------------------------- ω 2π L – Figure 5-4. Equations for Crystal Calculations The equation in Figure 5-4(b) yields the equivalent capacitance C at the operation frequency.
  • Page 150: Selecting Crystals

    CLOCK GENERATION AND POWER MANAGEMENT 5.1.1.2 Selecting Crystals When specifying crystals, consider these parameters: • Resonance and Load Capacitance — Crystals carry a parallel or series resonance specifi- cation. The two types do not differ in construction, just in test conditions and expected circuit application.
  • Page 151: Using An External Oscillator

    CLOCK GENERATION AND POWER MANAGEMENT An important consideration when using crystals is that the oscillator start correctly over the volt- age and temperature ranges expected in operation. Observe oscillator startup in the laboratory. Varying the load capacitors (within about ± 50%) can optimize startup characteristics versus sta- bility.
  • Page 152 CLOCK GENERATION AND POWER MANAGEMENT Reset may be either cold (power-up) or warm. Figure 5-6 illustrates a cold reset. Assert the RES- IN input during power supply and oscillator startup. The processor’s pins assume their reset pin states a maximum of 28 CLKIN periods after CLKIN and V stabilize.
  • Page 153 CLOCK GENERATION AND POWER MANAGEMENT CLKIN V cc and CLKIN stable to output valid 28 CLKIN periods (max) CLKOUT UCS, LCS GCS7:0, NPS T0OUT, T1OUT TXD1:0 HLDA, ALE RXI1, TXI1 DMAI0, DMAI1 A19:16 AD15:0, S2:0 RD, WR, DEN DT/R, LOCK RESIN RESOUT and CLKIN stable to...
  • Page 154 CLOCK GENERATION AND POWER MANAGEMENT CLKIN CLKOUT UCS, LCS GCS7:0, NPS T0OUT T1OUT TXD1:0 HLDA, ALE RXI1, TXI1 DMAI0 DMAI1 A19:16 AD15:0 S2:0, RD WR, DEN DT / R LOCK RESIN RESOUT Minimum RESIN RESIN low time 4 CLKOUT high to periods.
  • Page 155: Power Management

    CLOCK GENERATION AND POWER MANAGEMENT CLKIN RESIN RESYNC (Internal) CLKOUT RESOUT NOTES: 1. Setup of RESIN to falling CLKIN. 2. RESOUT goes active. 3. RESIN allowed to go inactive after minimum 4 CLKOUT cycles. 4. RESYNC pulse generated. 5. RESYNC pulse drives CLKOUT low, resynchronizing the clock generator. 6.
  • Page 156: Idle Mode

    CLOCK GENERATION AND POWER MANAGEMENT There are three power management modes: Idle, Powerdown and Power-Save. Power-Save mode is a clock generation function, while Idle and Powerdown modes are clock distribution functions. For this discussion, Active mode is the condition of no programmed power management. Active mode operation feeds the clock signal to the CPU core and all the integrated peripherals and pow- er consumption reaches its maximum for the application.
  • Page 157 PWRDN bit, otherwise Powerdown mode is not armed. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 5-9. Power Control Register 5-12...
  • Page 158: Bus Operation During Idle Mode

    CLOCK GENERATION AND POWER MANAGEMENT Halt Cycle T4 or TI CLKOUT Internal Peripheral Clock CPU Core Clock S2:0 A1119-0A Figure 5-10. Entering Idle Mode 5.2.1.2 Bus Operation During Idle Mode DMA requests, refresh requests and HOLD requests temporarily turn on the core clocks. If the processor needs to run a DMA cycle during Idle mode, the internal core clock begins to toggle on the falling CLKOUT edge three clocks after the processor samples the DMA request pin.
  • Page 159: Leaving Idle Mode

    CLOCK GENERATION AND POWER MANAGEMENT If the processor needs to run a refresh cycle during Idle mode, the internal core clock begins to toggle on the falling CLKOUT edge immediately after the down-counter reaches zero. After one idle T-state, the processor runs the refresh cycle. As with all other bus cycles, the BIU uses the ready, wait state generation and chip-select circuitry as necessary for refresh cycles during Idle mode.
  • Page 160: Example Idle Mode Initialization Code

    CLOCK GENERATION AND POWER MANAGEMENT Any unmasked interrupt received by the core will return the processor to Active mode. Interrupt requests pass through the Interrupt Control Unit with an interrupt resolution time for mask and priority level checking. Then, after 1½ clocks, the core clock begins toggling. It takes an addi- tional 6 CLKOUT cycles for the core to begin the interrupt vectoring sequence.
  • Page 161: Powerdown Mode

    CLOCK GENERATION AND POWER MANAGEMENT $mod186 name example_80C186_power_management_code ;FUNCTION: This function reduces CPU power consumption. SYNTAX: extern void far power_mgt(int mode); INPUTS: mode - 00 -> Active Mode 01 -> Powerdown Mode 02 -> Idle Mode 03 -> Active Mode ;...
  • Page 162: Entering Powerdown Mode

    CLOCK GENERATION AND POWER MANAGEMENT 5.2.2.1 Entering Powerdown Mode Powerdown mode is entered by executing the HLT instruction after setting the PWRDN bit in the Power Control Register (see Figure 5-9 on page 5-12). The HALT cycle turns off both the core and peripheral clocks and disables the crystal oscillator.
  • Page 163: Leaving Powerdown Mode

    CLOCK GENERATION AND POWER MANAGEMENT 5.2.2.2 Leaving Powerdown Mode An NMI, unmasked interrupt, or reset returns the processor to Active mode. Unlike other 80C186 Modular Core family members, the processor does not have clocked logic in the Interrupt Control Unit. If the device leaves Powerdown mode by an NMI or unmasked interrupt, a delay must follow the interrupt request to allow the crystal oscillator to stabilize before gating it to the internal phase clocks.
  • Page 164: Power-Save Mode

    CLOCK GENERATION AND POWER MANAGEMENT 0, Except when leaving Strong P-Channel Powerdown Pullup PDTMR Pin OSC_OK Weak N-Channel C PD Exit Powerdown Pulldown A1122-0A Figure 5-13. Powerdown Timer Circuit The first step in determining the proper C value is startup time characterization for the crystal oscillator circuit.
  • Page 165: Entering Power-Save Mode

    CLOCK GENERATION AND POWER MANAGEMENT Possible clock divisor settings are 1 (undivided), 4, 8, 16, 32 and 64. The divided frequency feeds the core, the integrated peripherals and CLKOUT. The processor operates at the divided clock rate exactly as if the crystal or external oscillator frequency were lower by the same amount. Since the processor is static, a lower limit clock frequency does not apply.
  • Page 166 1 0 1 By 64 1 1 0 Reserved 1 1 1 Reserved NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 5-14. Power-Save Register 5-21...
  • Page 167: Leaving Power-Save Mode

    CLOCK GENERATION AND POWER MANAGEMENT CLKOUT NOTES: 1. : Write to Power-Save Register (as viewed on the bus). 2. : Low-going edge of T3 starts new clock rate. A1124-0A Figure 5-15. Power-Save Clock Transition 5.2.3.2 Leaving Power-Save Mode Power-Save mode continues until one of three events occurs: execution clears the PSEN bit in the Power-Save Register, an unmasked interrupt occurs or an NMI occurs.
  • Page 168 CLOCK GENERATION AND POWER MANAGEMENT $mod186 name example_PSU_code ;FUNCTION: This function reduces CPU power consumption by dividing the CPU operating frequency by a divisor. SYNTAX: extern void far power_save(int divisor); INPUTS: divisor - This variable represents F0, F1 and F2 of PWRSAV.
  • Page 169: Implementing A Power Management Scheme

    CLOCK GENERATION AND POWER MANAGEMENT 5.2.4 Implementing a Power Management Scheme Table 5-2 summarizes the power management options available to the user. With three ways available to reduce power consumption, here are some guidelines: • Powerdown mode reduces power consumption by several orders of magnitude. If the application goes into and out of Powerdown frequently, the power reduction can probably offset the relatively long intervals spent leaving Powerdown mode.
  • Page 170 Chip-Select Unit...
  • Page 172: Chip-Select Unit Features And Benefits

    CHAPTER 6 CHIP-SELECT UNIT Every system requires some form of component-selection mechanism to enable the CPU to ac- cess a specific memory or peripheral device. The signal that selects the memory or peripheral de- vice is referred to as a chip-select. Besides selecting a specific device, each chip-select can be used to control the number of wait states inserted into the bus cycle.
  • Page 173: Chip-Select Unit Functional Overview

    CHIP-SELECT UNIT 27C256 74AC138 Selects 896K to 1M D7:0 Selects 768K to 896K A0:12 A1:13 D15:8 HLDA Selects 128K to 256K Selects 0 to 128K Chip-Selects Using Chip-Selects Using Addresses Directly Simple Decoder A1168-0A Figure 6-1. Common Chip-Select Generation Methods CHIP-SELECT UNIT FUNCTIONAL OVERVIEW The Chip-Select Unit (CSU) decodes bus cycle address and status information and enables the appropriate chip-select.
  • Page 174 CHIP-SELECT UNIT Ignore Stop Chip Select Address Enable Stop ISTOP CSEN Value Memory/IO Selector Stop < Value Comparator Internal Chip Address Address Select Shifter Start ≥ Value Comparator Start Peripheral Control Block Value Access Indicator A1160-0A Figure 6-2. Chip-Select Block Diagram Mapped to the upper memory address space;...
  • Page 175 CHIP-SELECT UNIT CLKOUT A15:0 Address Valid A19:16 GCS7:0 LCS, UCS Status S2:0 RD, WR A1150-0A Figure 6-3. Chip-Select Relative Timings A chip-select goes active when it meets all of the following criteria: The chip-select is enabled. The bus cycle status matches the programmed type (memory or I/O). The bus cycle address is equal to or greater than the start address value.
  • Page 176: Programming

    CHIP-SELECT UNIT Address Flash Ready Data 1023K Active For Memory Processor Top 1 KByte NOTE: 1. 15 Wait states automatically inserted. Bus READY must be provided. A1162-0A Figure 6-4. UCS Reset Configuration PROGRAMMING Two registers, START and STOP, determine the operating characteristics of each chip-select. The Peripheral Control Block defines the location of the Chip-Select Unit registers.
  • Page 177: Initialization Sequence

    CHIP-SELECT UNIT The START register (Figure 6-5) defines the starting address and the wait state requirements. The STOP register (Figure 6-6) defines the ending address and the bus ready, bus cycle and enable requirements. 6.4.1 Initialization Sequence Chip-selects do not have to be initialized in any specific order. However, the following guidelines help prevent a system failure.
  • Page 178 NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 6-5. START Register Definition...
  • Page 179 NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. The reset state of CSEN and ISTOP is ‘1’ for the UCSSP register.
  • Page 180 WS3:0. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. The reset state of CSEN and ISTOP is ‘1’ for the UCSSP register.
  • Page 181: Start Address

    CHIP-SELECT UNIT 6.4.2 Start Address The START register of each chip-select defines its starting (base) address. The start address value is compared to the ten most-significant address bits of the bus cycle. A bus cycle whose ten most- significant address bits are equal to or greater than the start address value causes the chip-select to go active.
  • Page 182: Enabling And Disabling Chip-Selects

    CHIP-SELECT UNIT In the previous equations, a stop value of 1023 (03FFH) results in a physical ending address of 0FFBFFH (memory) or 0FFBFH (I/O). These addresses do not represent the top of the memory or I/O address space. To have a chip-select enabled to the end of the physical address space, the ISTOP control bit must be set.
  • Page 183: Overlapping Chip-Selects

    CHIP-SELECT UNIT BUS READY READY Control Bit READY Wait Wait Wait State Value (WS3:0) State State Counter Ready A1165-0A Figure 6-7. Wait State and Ready Control Functions The STOP register defines the RDY control bit to extend bus cycles beyond fifteen wait states. The RDY control bit determines whether the bus cycle should complete normally (i.e., require bus ready) or unconditionally (i.e., ignore bus ready).
  • Page 184 CHIP-SELECT UNIT READY = 1 Wait Wait Maximum Minimum WS3:0 WS3:0 Wait State READY Complete Cycle A1166-0A Figure 6-8. Overlapping Chip-Selects 6-13...
  • Page 185: Memory Or I/O Bus Cycle Decoding

    When programming chip-selects active for I/O bus cycles, remember that eight bytes of I/O are reserved by Intel. These eight bytes (locations 00F8H through 00FFH) control the interface to an 80C187 math coprocessor. A chip-select can overlap this reserved space provided there is no in- tention of using the 80C187.
  • Page 186: Chip-Selects And Bus Hold

    CHIP-SELECT UNIT The GCS chip-select outputs are multiplexed with output port functions. The register that controls the multiplexed outputs resides in the I/O Port Unit. (See Table 13-1 on page 13-6 and Figure 13-4 on page 13-8.) CHIP-SELECTS AND BUS HOLD The Chip-Select Unit decodes only internally generated address and bus state information.
  • Page 187 CHIP-SELECT UNIT Processor READY EPROM SRAM Floppy 128K Disk Control A19:16 Addr DACK AD Bus 512K AD15:0 GCS0 GCS1 GCS2 A1157-0A Figure 6-10. Typical System 6-16...
  • Page 188 CHIP-SELECT UNIT TITLE (Chip-Select Unit Initialization) MOD186XREF NAME CSU_EXAMPLE_1 ; External reference from this module include(PCBMAP.INC) ;File declares Register ;Locations and names. ; Module equates ; Configuration equates TRUE EQU 0FFH FALSE EQU NOT TRUE READY EQU 0001H ;Bus ready control modifier CSEN EQU 0008H ;Chip-Select enable modifier...
  • Page 189 CHIP-SELECT UNIT DRAM_BASEEQU ;Window start address in Kbytes DRAM_SIZEEQU ;Window size in Kbytes DRAM_WAITEQU ;Wait states (change to match ;system) ;The GCS1# START and STOP register values are calculated using the above system ;constraints and the equations below GCS1ST_VALEQU (DRAM_BASE SHL 6) OR (DRAM_WAIT) GCS1SP_VALEQU (((DRAM_BASE) OR (DRAM_SIZE)) SHL 6) OR &...
  • Page 190 CHIP-SELECT UNIT ;SET UP CHIP SELECTS UCS# - EPROM Select LCS# - SRAM Select GCS1# - DRAM Select GCS2# - FLOPPY Select GCS0# - DACK Generator (programmed during DMA init) DX, UCSSP ;Finish setting up UCS# AX, UCSSP_VAL DX, AL ;Remember, byte writes work ok DX, LCSST ;Set up LCS#...
  • Page 191: Example 2: Detecting Attempts To Access Guarded Memory

    CHIP-SELECT UNIT ; DATA SEGMENT DATA SEGMENT PUBLIC ’DATA’ 256 DUP (?) ;Reserved for Interrupt Vectors ;Place additional memory variable here 500 DUP (?) ;Stack allocation STACK_TOP LABEL WORD DATA ENDS ;Program Ends Example 6-1. Initializing the Chip-Select Unit (Continued) 6.6.2 Example 2: Detecting Attempts to Access Guarded Memory A chip-select is configured to set an interrupt when the bus accesses a physical address region...
  • Page 192 Refresh Control Unit...
  • Page 194: Refresh Control Unit

    CHAPTER 7 REFRESH CONTROL UNIT The Refre h Control Unit (RCU) simplifies dynamic memory controller design with its integrat- ed address and clock counters. Figure 7-1 shows the relationship between the Bus Interface Unit and the Refresh Control Unit. Integrating the Refresh Control Unit into the processor allows an external DRAM controller to use chip-selects, wait state logic and status lines.
  • Page 195: Refresh Control Unit 7.1 The Role Of The Refresh Control Unit

    REFRESH CONTROL UNIT THE ROLE OF THE REFRESH CONTROL UNIT Like a DMA controller, the Refresh Control Unit runs bus cycles independent of CPU execution. Unlike a DMA controller, however, the Refresh Control Unit does not run bus cycle bursts nor does it transfer data.
  • Page 196 REFRESH CONTROL UNIT Refresh Control BIU Refresh Unit Operation Bus Operation Refresh Request Set "E" Bit Acknowledged Execute Load Counter Memory Read From Refresh Clock Interval Register Increment Address Counter = ? Remove Executed Request Every Clock Continue Decrement Counter Generated BIU Request A1265-0A...
  • Page 197: Refresh Addresses

    REFRESH CONTROL UNIT The BIU does not queue DRAM refresh requests. If the Refresh Control Unit generates another request before the BIU handles the present request, the BIU loses the present request. However, the address associated with the request is not lost. The refresh address changes only after the BIU runs a refresh bus cycle.
  • Page 198: Refresh Bus Cycles

    REFRESH CONTROL UNIT REFRESH BUS CYCLES Refresh bus cycles look exactly like ordinary memory read bus cycles except for the control sig- nals listed in Table 7-1. These signals can be ANDed in a DRAM controller to detect a refresh bus cycle.
  • Page 199 REFRESH CONTROL UNIT T3/TW CLKOUT Muxed Column Address S2:0 NOTES: 1. CAS is unnecessary for refresh cycles only. 2. WE is necessary for write cycles only. A1267-0A Figure 7-4. Suggested DRAM Control Signal Timing Relationships The cycle begins with presentation of the row address. RAS should go active on the falling edge of T2.
  • Page 200: Programming The Refresh Control Unit

    REFRESH CONTROL UNIT PROGRAMMING THE REFRESH CONTROL UNIT Given a specific processor operating frequency and information about the DRAMs in the system, the user can program the Refresh Control Unit registers. 7.7.1 Calculating the Refresh Interval DRAM data sheets show DRAM refresh requirements as a number of refresh cycles necessary and the maximum period to run the cycles.
  • Page 201: Refresh Base Address Register

    Uppermost address bits for DRAM refresh Base cycles. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 7-6. Refresh Base Address Register 7.7.2.2 Refresh Clock Interval Register The Refresh Clock Interval Register (Figure 7-7) defines the time between refresh requests.
  • Page 202: Refresh Control Register

    Sets the desired clock count between refresh Reload Value cycles. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 7-7. Refresh Clock Interval Register 7.7.2.3 Refresh Control Register Figure 7-8 shows the Refresh Control Register.
  • Page 203: Refresh Address Register

    The user cannot program these bits. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 7-8. Refresh Control Register 7.7.2.4...
  • Page 204: Programming Example

    A0 of the refresh address. This bit is always 1 and is read-only. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 7-9. Refresh Address Register 7.7.3 Programming Example Example 7-1 contains sample code to initialize the Refresh Control Unit.
  • Page 205 REFRESH CONTROL UNIT $mod186 name example_80C186_RCU_code ; FUNCTION: This function initializes the DRAM Refresh ; Control Unit to refresh the DRAM starting at dram_addr ; at clock_time intervals. ; SYNTAX: ; extern void far config_rcu(int dram_addr, int clock_time); ; INPUTS: dram_addr - Base address of DRAM to refresh clock_time - DRAM refresh rate...
  • Page 206: Refresh Operation And Bus Hold

    REFRESH CONTROL UNIT dx, RFBASE ;set upper 7 address bits ax, _dram_addr dx, al dx, RFTIME ;set clock pre_scaler ax, _clock_time dx, al dx, RFCON ;Enable RCU ax, Enable dx, al cx, 8 ;8 dummy cycles are ;required by DRAMs di, di ;before actual use _exercise_ram:...
  • Page 207 REFRESH CONTROL UNIT CLKOUT HOLD HLDA AD15:0 RD, WR, BHE, S2:0 DT / R, A19:16 NOTES: 1. HLDA is deasserted; signaling need to run DRAM refresh cycles less than T CLOV 2. External bus master terminates use of the bus. 3.
  • Page 208 Interrupt Control Unit...
  • Page 210 CHAPTER 8 INTERRUPT CONTROL UNIT The Interrupt Control Unit (ICU) is composed of two 8259A modules connected in cascade and three Interrupt Request Latch Registers (Figure 8-1). The slave 8259A module controls seven in- ternal interrupt sources and one external interrupt source (INT7). The master 8259A module con- trols seven external interrupt sources (INT6–INT0) and the slave module cascade request.
  • Page 211 INTERRUPT CONTROL UNIT Master 8259A INT0 INT1 INT2 INTA INT3 D7:0 INT4 INT5 INT6 INT7 Internal Interrupt Request Latch Registers Slave 8259A TMI0 TMI1 DMAI2 INTA DMAI3 D7:0 TMI2 RXI0 TXI0 INT7 CAS Bus Interrupt Requests From Integrated Peripherals A1217-0A Figure 8-1.
  • Page 212 INTERRUPT CONTROL UNIT Polling requires that the CPU check each peripheral device in the system periodically to see whether it requires servicing. It would not be unusual to poll a low-speed peripheral (a serial port, for instance) thousands of times before it required servicing. In most cases, the use of polling has a detrimental effect on system throughput.
  • Page 213: Interrupt Priority And Nesting

    INTERRUPT CONTROL UNIT Fetches the new CS and IP for the interrupt vector routine from the Interrupt Vector Table and begins executing from that point. INTERRUPT PRIORITY AND NESTING The priority of certain interrupts may change during program execution, or the program may wish to ignore some interrupt sources entirely.
  • Page 214 INTERRUPT CONTROL UNIT INTA Data Bus D7:0 Buffer Control Logic Read/Write Logic Internal Bus Cascade CAS2:0 Buffer/ Comparator Interrupt In-service Priority Request Register Resolver Register Interrupt Mask Register A1239-0A Figure 8-3. 8259A Module Block Diagram Pending interrupt requests are posted in the Interrupt Request Register. The Interrupt Request Register contains one bit for each of the eight Interrupt Request (IR) signals.
  • Page 215: A Typical Interrupt Sequence Using The 8259A Module

    INTERRUPT CONTROL UNIT The Interrupt Request Register bits feed into the Priority Resolver. The Priority Resolver decides which of the pending interrupt requests is the highest priority based on the programmed operating mode. The Priority Resolver controls the interrupt request line to the CPU. The Priority Resolver has a default priority scheme that places IR0 as the highest priority and IR7 as the lowest priority.
  • Page 216 INTERRUPT CONTROL UNIT In-Service Edge Latch Sense Latch CLEAR ISR Control LTIM Bit 0=Edge, 1= Level Logic SET ISR Priority Resolver Interrupt Request Non-Masked Latch Request INTA FREEZE Internal Data Bus MASTER CLEAR WRITE MASK FREEZE Other READ IMR Priority READ IRR Cells READ ISR...
  • Page 217 INTERRUPT CONTROL UNIT A typical sequence takes place as follows: A low-to-high transition on IR4 sets bit 4 in the Interrupt Request Register. The Priority Resolver checks whether any bits are set in the Interrupt Request Register that are of a higher priority than IR4. There are none. Because the 8259A module is in Fully Nested Mode, the Priority Resolver checks whether any bits are set in the In-Service Register that have priority greater than or equal to IR4.
  • Page 218: Interrupt Requests

    INTERRUPT CONTROL UNIT 8.3.2 Interrupt Requests The processing of an external interrupt begins with the assertion of an interrupt request signal on one of the IR lines. The signal first passes through the edge/level detection circuitry, then moves on to the Interrupt Request Register. 8.3.2.1 Edge and Level Triggering The IR lines are programmable for either edge or level triggering.
  • Page 219: Spurious Interrupts

    INTERRUPT CONTROL UNIT 8.3.2.3 Spurious Interrupts For both level- and edge-sensitive interrupts, a high value must be maintained on the IR line until after the falling edge of the second INTA pulse (see Figure 8-5). A spurious interrupt request is generated if this stipulation is not met.
  • Page 220: Default (Fixed) Priority

    INTERRUPT CONTROL UNIT 8.3.3.1 Default (Fixed) Priority After initialization, the 8259A module sets the priorities of the interrupt levels to the default con- dition, in which IR7 is the lowest priority and IR0 is the highest (Figure 8-6). For systems using fixed priority, the interrupt source with the highest priority is connected to IR0, the interrupt source with the second-highest priority is connected to IR1, and so on.
  • Page 221: Changing The Default Priority: Automatic Rotation

    INTERRUPT CONTROL UNIT 8.3.3.3 Changing the Default Priority: Automatic Rotation In some applications, a number of interrupting devices have equal priority. Automatic rotation ensures that devices of equal priority get equal shares of CPU resources. When programmed for automatic rotation, the 8259A module automatically assigns an IR line the lowest priority after the service routine for that interrupt has completed (and the EOI com- mand has been sent).
  • Page 222: Clearing The In-Service Bits: Non-Specific End-Of-Interrupt

    INTERRUPT CONTROL UNIT More than one In-Service bit can be set concurrently. Consider the case in which a low priority interrupt handler is interrupted by a higher-priority interrupt request (the interrupts are nested). The In-Service bits for both interrupt sources are set when the higher-priority interrupt is ac- knowledged.
  • Page 223: Masking Interrupts

    INTERRUPT CONTROL UNIT Use of Automatic EOI Mode precludes a fully nested interrupt structure. When Automatic EIO Mode is selected, the In-Service bit is cleared before the handler begins execution. As soon as the In-Service bit is cleared, any unmasked source (of any priority) can interrupt the handler. Automatic EOI Mode can be used only in a master 8259A in a cascaded system.
  • Page 224 INTERRUPT CONTROL UNIT Master 8259A From INTA Slave 8259A INTA A1245-0A Figure 8-9. Typical Cascade Connection 8-15...
  • Page 225: The Cascaded Interrupt Acknowledge Cycle: An Example

    INTERRUPT CONTROL UNIT 8.3.6.2 The Cascaded Interrupt Acknowledge Cycle: An Example The following example illustrates the interaction between master and slave 8259A modules in a cascaded configuration. We assume the following conditions: • The master 8259A module is programmed for cascade operation, a slave on IR7, default priority and edge-triggered mode.
  • Page 226: Master Cascade Configuration

    INTERRUPT CONTROL UNIT 10. On the second falling edge of INTA, the slave 8259A module drives the interrupt type corresponding to IR2 on the data bus. The CAS2:0 lines return to their inactive low state and the slave 8259A module floats its data bus when INTA goes high. The interrupt request signal from the master 8259A module to the CPU goes inactive (low).
  • Page 227: Spurious Interrupts In A Cascaded System

    INTERRUPT CONTROL UNIT 8.3.6.6 Spurious Interrupts in a Cascaded System A spurious interrupt on a master IR line that is uncascaded will generate a spurious IR type 7. The CAS lines remain inactive when a spurious interrupt is acknowledged (a slave connected to IR7 will not be addressed).
  • Page 228: Alternate Modes Of Operation: Special Mask Mode

    INTERRUPT CONTROL UNIT 8.3.7 Alternate Modes of Operation: Special Mask Mode Some applications require an interrupt handler to dynamically alter the system priority structure. For example, the handler may need to inhibit lower-priority interrupts during a portion of its ex- ecution but enable some of them during another portion of the code.
  • Page 229: Alternate Modes Of Operation: The Poll Command

    INTERRUPT CONTROL UNIT 8.3.9 Alternate Modes of Operation: The Poll Command Conventional polling requires that the CPU check each peripheral device to determine whether it needs servicing. Polling can also be accomplished with an 8259A module by using the Poll com- mand.
  • Page 230: Programming Sequence And Register Addressing

    INTERRUPT CONTROL UNIT 8.4.2 Programming Sequence and Register Addressing All of the 8259A module registers reside within an address window of two bytes. Write access to individual registers is controlled by a combination of the following: • the address of the register (state of the A0 address line on the 8259A module) •...
  • Page 231 INTERRUPT CONTROL UNIT Initialization begins with the writing of ICW1. ICW1 is accessed whenever a write to the 8259A module occurs with A0=0 (MPICP0 or SPICP0) and data bit D4=1. The following actions occur within the 8259A module when ICW1 is written: •...
  • Page 232: Icw1: Edge/Level Mode, Single/Cascade Mode

    INTERRUPT CONTROL UNIT Begin Initialization Write ICW1 Write ICW2 Cascade Mode? Write ICW3 Need ICW4? Write ICW4 Initialization Complete A1219-0A Figure 8-11. 8259A Module Initialization Sequence 8.4.3.2 ICW1: Edge/Level Mode, Single/Cascade Mode The bit positions and definitions for ICW1 are summarized in Figure 8-12. 8-23...
  • Page 233 80C188EC systems. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-12. ICW1 Register The LTIM bit controls the edge detection circuitry on the interrupt request input lines. There is no provision for setting the mode of the individual IR lines.
  • Page 234: Icw2: Base Interrupt Type

    T2:0 are automatically set equal to the interrupt request line that is being acknowledged. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-13. ICW2 Register NOTE Pay strict attention to reserved interrupt types (see Figure 2-25 on page 2-40) when assigning a base interrupt type to an 8259A module.
  • Page 235: Icw3: Cascaded Pins/Slave Address

    INTERRUPT CONTROL UNIT 8.4.3.4 ICW3: Cascaded Pins/Slave Address The function of ICW3 differs between 8259A modules configured as masters and those config- ured as slaves. ICW3 is accepted by the 8259A module only if it has been programmed for cas- cade mode.
  • Page 236 NOTE: The S7 bit must be set in the master 8259A module for the 80C186EC/C188EC. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-14. ICW3 Register — Master Cascade Configuration 8-27...
  • Page 237 80C186EC/C188EC must be set to an ID of 7 (111 binary). NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-15. ICW3 Register — Slave ID 8-28...
  • Page 238 Failure to do so will cause system failure and may cause system damage. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-16. ICW4 Register 8-29...
  • Page 239: The Operation Command Words

    INTERRUPT CONTROL UNIT 8.4.4 The Operation Command Words The 8259A is reprogrammed during program execution by using the Operation Command Words. The Operation Command Words can be sent at any time after initialization of the 8259A module is complete. The three Operation Command Words (OCW1, OCW2 and OCW3) are ad- dressed through a combination of the A1 (register address) line and the state of data bits D3 and D4 (see Table 8-1).
  • Page 240 NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-17. OCW1 — Interrupt Mask Register 8-31...
  • Page 241 “don’t care” values. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-18. OCW2 Register Table 8-2. OCW2 Instruction Field Decoding...
  • Page 242 INTERRUPT CONTROL UNIT Table 8-2. OCW2 Instruction Field Decoding (Continued) Command Rotate on Non-Specific EOI Command Set Priority (Specific Rotation) * Rotate on Specific EOI Command * * These commands use the L2:0 field The Rotate in Automatic EOI Mode commands control priority rotation when the 8259A module is programmed (in ICW4) for Automatic EOI Mode.
  • Page 243: Special Mask Mode, Poll Mode And Register Reading: Ocw3

    Service Register is read; when RSEL is cleared, the Interrupt Request Register is read. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-19. OCW3 Register 8-34...
  • Page 244 INTERRUPT CONTROL UNIT The ESMM (Enable Special Mask Mode) and SMM (Special Mask Mode) bits are used to place the 8259A module into Special Mask Mode. Special Mask Mode is selected by setting the SMM bit. The SMM bit can be modified (set or cleared) only when the ESMM bit is set. The ERR (Enable Read Register) and RSEL (Register Select) bits select which register is read from the 8259A module during read cycles that have A0=0 (A0=1 reads the Interrupt Mask Reg- ister).
  • Page 245: Module Integration: The 80C186Ec Interrupt Control Unit

    INTERRUPT CONTROL UNIT MODULE INTEGRATION: THE 80C186EC INTERRUPT CONTROL UNIT The 80C186EC/C188EC Interrupt Control Unit uses two 8259A modules with additional support circuitry. This section describes the integration of the two 8259A modules and the programming of the Interrupt Control Unit. 8.5.1 Internal Interrupt Sources The 80C186/C188EC has a total of eleven internal interrupt requests from the on-chip peripher-...
  • Page 246: Directly Supported Internal Interrupt Sources

    INTERRUPT CONTROL UNIT Interrupt Request Latch Bit Internal Interrupt Request To 8259A Module or Port MUX Clear Internal Request (From CLEAR IRL Control Logic) CLKOUT Internal Interrupt Request Output of Interrupt Request Latch A1230-0A Figure 8-21. Interrupt Request Latch Register Function 8.5.1.1 Directly Supported Internal Interrupt Sources Seven of the eleven internal interrupt sources are directly supported by the Interrupt Control Unit.
  • Page 247: Indirectly Supported Internal Interrupt Sources

    INTERRUPT CONTROL UNIT Timer 0 Highest Priority Timer 1 DMA Channel 2 DMA Channel 3 Timer 2 Serial Channel 0 Receive Serial Channel 0 Transmit INT7 Pin Lowest Priority A1231-0A Figure 8-22. Default Slave 8259 Module Priority 8.5.1.2 Indirectly Supported Internal Interrupt Sources The interrupt request lines for DMA channel 0 and DMA channel 1 and the receive and transmit interrupts for serial channel 1 are not tied internally to the Interrupt Control Unit.
  • Page 248: Using The Interrupt Request Latch Registers

    INTERRUPT CONTROL UNIT To Slave 8259A Module DMAI3 DMAI2 Interrupt Request DMAI1 Latch P3.3/DMAI1 Register Interrupt DMAI0 P3.2/DMAI0 Requests Port 3 From On-Chip TXI1 P3.1/TXI1 Peripherals Serial RXI1 Interrupt P3.0/RXI1 Request TXI0 Latch Register RXI0 Internal Data Bus A1232-0A Figure 8-23. Multiplexed Interrupt Requests 8.5.1.3 Using the Interrupt Request Latch Registers An interrupt handler for an on-board peripheral must clear that peripheral’s Interrupt Request...
  • Page 249: Using The Interrupt Request Latch Registers To Debug Interrupt Handlers

    These bits are write only. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-24. DMA Interrupt Request Latch Register 8-40...
  • Page 250 These bits are write only. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-25. Serial Communications Interrupt Request Latch Register 8-41...
  • Page 251: Hardware Considerations With The Interrupt Control Unit

    NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-26. Timer Interrupt Request Latch Register HARDWARE CONSIDERATIONS WITH THE INTERRUPT CONTROL UNIT This section covers hardware interface information for the Interrupt Control Unit.
  • Page 252: Interrupt Latency And Response Time

    INTERRUPT CONTROL UNIT 8.6.1 Interrupt Latency and Response Time Interrupt latency is the time required for the CPU to begin the interrupt acknowledge sequence once an unmasked external interrupt is presented. Interrupt response time is the amount of time necessary to complete the interrupt acknowledge cycle and transfer program control to the inter- rupt handler.
  • Page 253: Ready Generation

    INT6:0 + INT7 = 57 total IRs). Polling may be used to extend I/O handling capability be- yond 57 sources. This section covers external cascading and applies to all of the 8259A family devices. Intel rec- ommends the use of the 82C59A-2 device for cascading to the 80C186EC/C188EC family due to its higher speed and lower power consumption compared with the older NMOS 8259A devic- A typical connection for an external cascaded 82C59A-2 device is shown in Figure 8-29.
  • Page 254: The External Inta Cycle

    SP/EN INT6 AD15/CAS2 AD14/CAS1 AD13/CAS0 Note: Latched A0 is used for 80C188EC, latched A1 is used for 80C186EC A1238-0A Figure 8-29. Typical Cascade Connection for 82C59A-2 8.6.4.1 The External INTA Cycle Every interrupt acknowledge (INTA) cycle, including those that access the internal 8259A mod- ules, is visible on the external processor pins.
  • Page 255: Timing Constraints

    There are several timing constraints to be aware of when connecting an external 8259 device. The following discussion is based on an analysis of the 82C59A-2 device specifications. The 82C59A-2 is the fastest 8259A family device currently available from Intel. Minimum RD/INTA Pulse Width (T...
  • Page 256: Module Examples

    INTERRUPT CONTROL UNIT Non-Alike Access Recovery Time (T ) refers to the recovery time required by the 82C59A-2 CHCL between accesses of different types (e.g., a RD followed by a WR or a WR followed by an INTA). This problem is more complicated than the back-to-back read or write recovery time because the programmer does not typically have control over the INTA signal.
  • Page 257: Interrupt Control Unit

    INTERRUPT CONTROL UNIT ;We begin with a type 28h (Type 40) interrupt. AX, AX ;Clear AX DS, AX ;Data seg points to vector table AX, OFFSET TIM0_HANDLER BX, 28H*4 DS:[BX], AX ;Store the offset of the handler AX, SEG TIM0_HANDLER BX, 28H*4+2 DS:[BX], AX ;Store segment of the handler...
  • Page 258 INTERRUPT CONTROL UNIT ;Now start the master initialization DX, MPICP0 ;ICW1 for the slave is accessed ;thru MPICP0 AH, AH ;Clear reserved bits AL, 10001B ;Edge trigger, cascade mode, ;IC4 required DX, AL ;Now set base interrupt type at 20H (Type 32) for the master module in ICW2. ;This creates a contiguous block for the interrupt control unit ;from type 20H to type 2FH.
  • Page 259 INTERRUPT CONTROL UNIT ;The following is a template for an interrupt handler for the 80C186EC/C188EC: INT_HNDLERS SEGMENT ASSUME CS:INT_HNDLRS TIM0_HANDLER PROC FAR ;Necessary to nest interrupts ;Handler code would be inserted here. DX, TIMIRL ;Need to clear IR for AX, 0100H ;TIMER 0 (MSK0=1, TIR0=0) DX, AL ;Request is now deasserted...
  • Page 260 INTERRUPT CONTROL UNIT ;The following section of code shows the polling process ;for the 8259A modules... ;For brevity, the Register EQUates are not shown. POLL_EXAMPLE SEGMENT ASSUME CS:POLL_EXAMPLE DX, SPICP0 ;POLL Command issued thru OCW3 AX, 0CH ;POLL=1 and D5:4=01 DX, AL ;Issue POLL Command ;The slave 8259A will deposit the poll status byte on the...
  • Page 262 Timer/Counter Unit...
  • Page 264: Functional Overview

    CHAPTER 9 TIMER/COUNTER UNIT The Timer/Counter Unit can be used in many applications. Some of these applications include a real-time clock, a square-wave generator and a digital one-shot. All of these can be implemented in a system design. A real-time clock can be used to update time-dependent memory variables. A square-wave generator can be used to provide a system clock tick for peripheral devices.
  • Page 265 TIMER/COUNTER UNIT T0 In T1 In Transition Latch/ Transition Latch/ Synchronizer Synchronizer Timer 0 Registers Output Latch Counter Timer 1 Element Registers Output Latch Timer 2 Registers Interrupt Latch Clock A1292-0A Figure 9-1. Timer/Counter Unit Block Diagram...
  • Page 266 TIMER/COUNTER UNIT Timer 0 Timer 1 Timer 2 Timer 0 Timer 1 Timer 2 Timer 0 Serviced Serviced Serviced Dead Serviced Serviced Serviced Dead Serviced T0IN T1IN T0OUT T1OUT NOTES: 1. T0IN resolution time (setup time met). 2. T1IN resolution time (setup time not met). 3.
  • Page 267 TIMER/COUNTER UNIT Timer Enabled Done Start (EN = 1) External Clocking (EXT = 1) Retrigger (RTG = 1) Lo to Hi Lo to Hi Timer Input transition on input transition on input at High Level pin since last pin since last service service Clear Count...
  • Page 268 TIMER/COUNTER UNIT Continued From "A" Alternating Maxcount Regs (ALT = 1) Using Counter = (Use"A") (Use"B") Maxcount A Compare "A" (RIU = 0) Counter = Counter = Compare "A" Compare "B" Done Pulse TOUT Pin Set RIU Bit Clear RIU Bit Low For 1 Clock TOUT Pin Driven Low TOUT Pin Driven High...
  • Page 269: Programming The Timer/Counter Unit

    TIMER/COUNTER UNIT When configured for internal clocking, the Timer/Counter Unit uses the input pins either to en- able timer counting or to retrigger the associated timer. Externally, a timer increments on low-to- high transitions on its input pin (up to ¼ CLKOUT frequency). Timers 0 and 1 each have a single output pin.
  • Page 270 If MC is clear, the counter has not reached a maximum count. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 9-5. Timer 0 and Timer 1 Control Registers...
  • Page 271 (clear the EN bit) after each counting sequence. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 9-5. Timer 0 and Timer 1 Control Registers (Continued)
  • Page 272: Timer 2 Control Register

    Clear to disable the counter (clear the EN bit) after each counting sequence. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 9-6. Timer 2 Control Register...
  • Page 273 TIMER/COUNTER UNIT Register Name: Timer Count Register Register Mnemonic: T0CNT, T1CNT, T2CNT Register Function: Contains the current timer count. A1299-0A Reset Bit Name Function Mnemonic State TC15:0 Timer XXXXH Contains the current count of the associated Count Value timer. Figure 9-7. Timer Count Registers 9-10...
  • Page 274: Initialization Sequence

    TIMER/COUNTER UNIT Register Name: Timer Maxcount Compare Register Register Mnemonic: T0CMPA, T0CMPB, T1CMPA, T1CMPB, T2CMPA Register Function: Contains timer maximum count value. A1300-0A Reset Bit Name Function Mnemonic State TC15:0 Timer XXXXH Contains the maximum value a timer will count Compare to before resetting its Count register to zero.
  • Page 275: Clock Sources

    TIMER/COUNTER UNIT 9.2.2 Clock Sources The 16-bit Timer Count register increments once for each timer event. A timer event can be a low-to-high transition on a timer input pin (Timers 0 and 1), a pulse generated every fourth CPU clock (all timers) or a timeout of Timer 2 (Timers 0 and 1). Up to 65536 (2 ) events can be count- Timers 0 and 1 can be programmed to count low-to-high transitions on their input pins as timer events by setting the External (EXT) bit in their control registers.
  • Page 276: Retriggering

    TIMER/COUNTER UNIT The timer counting from its initial count (usually zero) to its maximum count (either Maxcount Compare A or B) and resetting to zero defines one timing cycle. A Maxcount Compare value of 0 implies a maximum count of 65536, a Maxcount Compare value of 1 implies a maximum count of 1, etc.
  • Page 277: Pulsed And Variable Duty Cycle Output

    TIMER/COUNTER UNIT Table 9-2. Timer Retriggering Timer Operation Timer counts internal events, if input pin remains high. Timer counts internal events; count resets to zero on every low-to-high transition on the input pin. Timer input acts as clock source. When the EXT bit is clear and the RTG bit is set, every low-to-high transition on the timer input pin causes the Count register to reset to zero.
  • Page 278: Enabling/Disabling Counters

    TIMER/COUNTER UNIT Timer 0 Serviced Internal Count Value Maxcount - 1 TxOUT Pin NOTE: 1. T CLOV1 A1301-0A Figure 9-9. TxOUT Signal Timing In dual maximum count mode, the timer output pin indicates which Maxcount Compare register is currently in use. A low output indicates Maxcount Compare B, and a high output indicates Maxcount Compare A (see Figure 9-4 on page 9-6).
  • Page 279: Timer Interrupts

    TIMER/COUNTER UNIT The input pins for Timers 0 and 1 provide an alternate method for enabling and disabling timer counting. When using internal clocking, the input pin can be programmed either to enable the tim- er or to reset the timer count, depending on the state of the Retrigger (RTG) bit in the control reg- ister.
  • Page 280: Synchronization And Maximum Frequency

    TIMER/COUNTER UNIT 9.3.2 Synchronization and Maximum Frequency All timer inputs are latched and synchronized with the CPU clock. Because of the internal logic required to synchronize the external signals, and the multiplexing of the counter element, the Timer/Counter Unit can operate only up to ¼ of the CLKOUT frequency. Clocking at greater fre- quencies will result in missed clocks.
  • Page 281 TIMER/COUNTER UNIT $mod186 name example_80186_family_timer_code ;FUNCTION: This function sets up the timer and interrupt controller to cause the timer to generate an interrupt every 10 milliseconds and to service interrupts to implement a real time clock. Timer 2 is used in this example because no input or output signals are required.
  • Page 282 TIMER/COUNTER UNIT lib_80186 segment public ’code’ assume cs:lib_80186, ds:data public _set_time _set_time proc far push ;save caller’s bp bp, sp ;get current top of stack hour equ word ptr[bp+6] ;get parameters off stack minute equ word ptr[bp+8] second equ word ptr[bp+10] T2Compare equ word ptr[bp+12] push ;save registers used...
  • Page 283 TIMER/COUNTER UNIT ;enable interrupts ;restore saved registers ;restore caller’s bp _set_time endp timer_2_interrupt_routine proc far push ;save registers used push _msec, 99 ;has 1 sec passed? bump_second ;if above or equal... _msec short reset_int_ctl bump_second: _msec, 0 ;reset millisecond _minute, 59 ;has 1 minute passed? bump_minute _second...
  • Page 284 TIMER/COUNTER UNIT $mod186 name example_timer1_square_wave_code ;FUNCTION: This function generates a square wave of given frequency and duty cycle on Timer 1 output pin. SYNTAX: extern void far clock(int mark, int space) INPUTS: mark - This is the mark (1) time. space - This is the space (0) time.
  • Page 285 TIMER/COUNTER UNIT ;restore saved registers ;restore caller’s bp _clock endp lib_80186 ends Example 9-2. Configuring a Square-Wave Generator (Continued) $mod186 name example_timer1_1_shot_code ; FUNCTION: This function generates an active-low one-shot pulse on Timer 1 output pin. ; SYNTAX: extern void far one_shot(int CMPB); ;...
  • Page 286 TIMER/COUNTER UNIT _CMPB equ word ptr[bp+6] ;get parameter off the stack push ;save registers that will be push ;modified dx, T1CNT ;Clear Timer 1 Counter ax, ax dx, al dx, T1CMPA ;set time before t_shot to 0 ax, 1 dx, al dx, T1CMPB ;set pulse time ax, _CMPB...
  • Page 288 Direct Memory Access Unit...
  • Page 290: The Dma Transfer

    CHAPTER 10 DIRECT MEMORY ACCESS UNIT In many applications, large blocks of data must be transferred between memory and I/O space. A disk drive, for example, usually reads and writes data in blocks that may be thousands of bytes long. If the CPU were required to handle each byte of the transfer, the main tasks would suffer a severe performance penalty.
  • Page 291 DIRECT MEMORY ACCESS UNIT When the DMA request is granted, the Bus Interface Unit provides the bus signals for the DMA transfer, while the DMA channel provides the address information for the source and destination devices. The DMA Unit does not provide a discrete DMA acknowledge signal, unlike other DMA controller chips (an acknowledge can be synthesized, however).
  • Page 292: Dma Transfer Directions

    DIRECT MEMORY ACCESS UNIT 10.1.1.1 DMA Transfer Directions The source and destination addresses for a DMA transfer are programmable and can be in either memory or I/O space. DMA transfers can be programmed for any of the following four direc- tions: •...
  • Page 293: External Requests

    DIRECT MEMORY ACCESS UNIT 10.1.4 External Requests External DMA requests are asserted on the DRQ pins. The DRQ pins are sampled on the falling edge of CLKOUT. It takes a minimum of four clocks before the DMA cycle is initiated by the BIU (see Figure 10-2).
  • Page 294: Source Synchronization

    DIRECT MEMORY ACCESS UNIT 10.1.4.1 Source Synchronization A typical source-synchronized transfer is shown in Figure 10-3. Most DMA-driven peripherals deassert their DRQ line only after the DMA transfer has begun. The DRQ signal must be deas- serted at least four clocks before the end of the DMA transfer (at the T1 state of the deposit phase) to prevent another DMA cycle from occurring.
  • Page 295: Internal Requests

    DIRECT MEMORY ACCESS UNIT Fetch Cycle Deposit Cycle CLKOUT (Case 1) (Case 2) NOTES: 1. Current destination synchronized transfer will not be immediately followed by another DMA transfer. 2. Current destination synchronized transfer will be immediately followed by another DMA transfer. A1189-0A Figure 10-4.
  • Page 296: Serial Communications Unit Transfers

    DIRECT MEMORY ACCESS UNIT 10.1.5.3 Serial Communications Unit Transfers The Serial Communications Unit has two channels, each with its own receiver and transmitter. Each of the DMA channels is assigned a Serial Communications Unit channel as follows: • DMA channel 0 supports the serial port 0 transmitter (TX0). •...
  • Page 297: Termination At Terminal Count

    DIRECT MEMORY ACCESS UNIT 10.1.7.1 Termination at Terminal Count When programmed to terminate on terminal count, the DMA channel disarms itself when the transfer count value reaches zero. No further DMA transfers take place on the channel until it is re-armed by direct programming.
  • Page 298: The Two-Channel Dma Module

    DIRECT MEMORY ACCESS UNIT The Chip-Select Unit monitors the BIU addresses to determine which chip-select, if any, to acti- vate. Because the DMA Unit uses the BIU, chip-selects are active for DMA cycles. If a DMA channel accesses a region of memory or I/O space within a chip-select’s programmed range, then that chip-select is asserted during the cycle.
  • Page 299 DIRECT MEMORY ACCESS UNIT Module Timer 2 DMA Request Internal - DMA Inter-module Request Arbitration Multiplexer Logic Timer 2 Timer 2 Request Request Source Pointer Source Pointer Destination Pointer Destination Pointer Channel 0 Channel 1 Control Logic Control Logic DRQ Pin DRQ Pin A1540-01 Figure 10-5.
  • Page 300 DIRECT MEMORY ACCESS UNIT Both Requests Asserted Channel Etc. Priority Channel 1 Channel 0 Channel 1 Channel 0 Synch Channel Etc. Priority High Channel 0 Channel 0 Channel 1 Channel 1 Synch Channel 0 Completes All Transfers Channel Etc. Priority High Channel 0 Channel 1...
  • Page 301: Dma Module Integration

    DIRECT MEMORY ACCESS UNIT Timer 2 DMA Request Internal DMA Request Serial Transmitter For Channel 0 DMA Request Internal DMA Request For Channel 1 Serial Receiver DMA Request Select (From Internal DMA Request Multiplexer Register) A1183-0A Figure 10-7. Internal DMA Request Multiplexer 10.1.11 DMA Module Integration The DMA Unit of the 80C186EC/C188EC consists of two DMA modules (a total of four chan- nels) and the Inter-Module Arbitration Circuitry (see Figure 10-8).
  • Page 302: Dma Unit Structure

    DIRECT MEMORY ACCESS UNIT 10.1.11.1 DMA Unit Structure The two DMA modules within the DMA Unit are referred to as module A and module B. Both modules function identically. Table 10-1 includes naming and signal connection information for each channel. Table 10-1.
  • Page 303 DIRECT MEMORY ACCESS UNIT BIU Request Inter-Module Arbitration Logic Module A Module B Request Request Inter-Channel Arbitration Inter-Channel Arbitration Internal Request Multiplexer Internal Request Multiplexer Channel 0 Channel 1 Channel 0 Channel 1 Module A Module B DRQ0 DRQ1 DRQ2 DRQ3 A1184-0A Figure 10-8.
  • Page 304: Programming The Dma Unit

    DIRECT MEMORY ACCESS UNIT Channel arbitration within the DMA Unit first begins on the module level. Each module priori- tizes its two DMA requests (if active) and then presents a module request to the Inter-Module Ar- bitration Logic. If both modules are requesting transfers, the Inter-Module Arbitration Logic decides which of the two modules has highest priority and grants that module control of the bus.
  • Page 305 DMA transfer. Address NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-9. DMA Source Pointer (High-Order Bits) 10-16...
  • Page 306 DIRECT MEMORY ACCESS UNIT Register Name: DMA Source Address Pointer (Low) Register Mnemonic: DxSRCL Register Function: Contains the lower 16 bits of the DMA Source pointer. A1177-0A Reset Bit Name Function Mnemonic State DSA15:0 XXXXH DSA15:0 are driven on the lower 16 bits of the Source address bus during the fetch phase of a DMA Address...
  • Page 307 DMA transfer. Address NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-11. DMA Destination Pointer (High-Order Bits) 10-18...
  • Page 308: Selecting Byte Or Word Size Transfers

    DIRECT MEMORY ACCESS UNIT Register Name: DMA Destination Address Pointer (Low) Register Mnemonic: DxDSTL Register Function: Contains the lower 16 bits of the DMA Destination pointer. A1179-0A Reset Bit Name Function Mnemonic State DDA15:0 XXXXH DDA15:0 are driven on the lower 16 bits of the Destination address bus during the deposit phase of a DMA Address...
  • Page 309: Dma Control Register

    (See Note.) NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. A pointer remains constant if its increment and decrement bits are equal.
  • Page 310: Dma Control Register

    (SYN1:0 = 01). NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-13. DMA Control Register (Continued) 10-21...
  • Page 311: Selecting The Source Of Dma Requests

    Select device ignore the WORD bit. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-13. DMA Control Register (Continued) 10.2.1.3 Selecting the Source of DMA Requests DMA requests can come from either an internal source or an external source.
  • Page 312: Arming The Dma Channel

    DIRECT MEMORY ACCESS UNIT When internal DMA requests are selected, the source of the internal request must be pro- grammed. The Internal DMA Request Multiplexer is programmable on a module basis only. The two channels in a module can be programmed to both respond to Timer 2 or both respond to the serial port.
  • Page 313: Programming The Transfer Count Options

    Module A priority. Priority NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-14. DMA Module Priority Register 10.2.1.6 Programming the Transfer Count Options...
  • Page 314: Generating Interrupts On Terminal Count

    DIRECT MEMORY ACCESS UNIT The transfer count (the number of transfers desired) is written to the DMA Transfer Count Reg- ister. The Transfer Count Register is 16 bits wide, limiting the total number of transfers for a channel to 65,536 (without reprogramming). The Transfer Count Register is decremented by one after each transfer (for both byte and word transfers).
  • Page 315: Setting The Relative Priority Of A Channel

    DIRECT MEMORY ACCESS UNIT 10.2.1.8 Setting the Relative Priority of a Channel The priority of a channel within a module is controlled by the Priority bit in the DMA Control Register (Figure 10-13 on page 10-20). A channel may be assigned either high or low priority. If both channels are programmed to the same priority (i.e., both high or both low), the channels ro- tate priority.
  • Page 316: Suspension Of Dma Transfers Using The Dma Halt Bits

    DIRECT MEMORY ACCESS UNIT 10.2.4 Suspension of DMA Transfers Using the DMA Halt Bits The DMA Module HALT Register (Figure 10-16) contains three bits that allow the system soft- ware to suspend DMA transfers temporarily. The HNMI bit is set automatically whenever the CPU receives an NMI .
  • Page 317: Hardware Considerations And The Dma Unit

    Module A NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-16. DMA Module HALT Register 10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT This section covers hardware interfacing and performance factors for the DMA Unit.
  • Page 318: Drq Pin Timing Requirements

    DIRECT MEMORY ACCESS UNIT 10.3.1 DRQ Pin Timing Requirements The DRQ pins are sampled on the falling edge of CLKOUT. The DRQ pins must be set up a min- imum of T before CLKOUT falling and must be held a minimum of T after CLKOUT CLIS CLIH...
  • Page 319: Generating A Dma Acknowledge

    DIRECT MEMORY ACCESS UNIT Because of its 8-bit data bus, the 80C188 Modular Core can transfer only one byte per DMA cy- cle. Therefore, the maximum transfer rates for the 80C188 Modular Core are half those calculated by the equations for the 80C186 Modular Core. 10.3.4 Generating a DMA Acknowledge The DMA channels do not provide a distinct DMA acknowledge signal.
  • Page 320 DIRECT MEMORY ACCESS UNIT $MOD186 name DMA_EXAMPLE_1 ; This example shows code necessary to set up two DMA channels. ; One channel performs an unsynchronized transfer from memory to memory. ; The second channel is used by a hard disk controller located in ;...
  • Page 321 DIRECT MEMORY ACCESS UNIT DX, D0DSTH AX, BX ; GET HIGH NIBBLE DX, AX ; THE POINTER ADDRESSES HAVE BEEN SET UP. NOW WE SET UP THE TRANSFER COUNT. AX, 29 ; THE MESSAGE IS 29 BYTES LONG. DX, D0TC ;...
  • Page 322 DIRECT MEMORY ACCESS UNIT AX, 512 ; THE DISK READS IN 512 BYTE SECTORS DX, D1TC ; XFER COUNT REG DX, AX ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS: DESTINATION SOURCE ----------- ------ MEMORY SPACE I/O SPACE INCREMENT PTR CONSTANT PTR...
  • Page 323 DIRECT MEMORY ACCESS UNIT $mod186 name DMA_WITH_SCU ; The following example initializes the DMA unit to perform ; DMA-driven serial transfers. ; It is assumed that the serial port has been initialized for ; Mode 1 asynchronous transfers. Register mnemonics are assumed ;...
  • Page 324 DIRECT MEMORY ACCESS UNIT AX, AX ; HIGH ADDRESS=0 DX, D2DSTH DX, AX ; THE POINTER ADDRESSES HAVE BEEN SET UP. NOW WE SET UP THE TRANSFER COUNT. AX, 25 ; THE MESSAGE IS 25 BYTES LONG. DX, D2TC ; XFER COUNT REG DX, AX ;...
  • Page 325 DIRECT MEMORY ACCESS UNIT AX, AX ; HIGH ADDRESS=0 DX, D3SRCH DX, AX ; THE POINTER ADDRESSES HAVE BEEN SET UP. NOW WE SET UP THE TRANSFER COUNT. AX, 128 ; INTERRUPT AFTER 128 BYTES DX, D3TC ; ARE RECEIVED. DX, AX ;...
  • Page 326 DIRECT MEMORY ACCESS UNIT $mod186 name DMA_EXAMPLE_1 ; This example sets up the DMA Unit to perform a transfer from memory to ; I/O space every 22 uS. The data is sent to an A/D converter. ; It is assumed that the constants for PCB register addresses are ;...
  • Page 327 DIRECT MEMORY ACCESS UNIT ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS: DESTINATION SOURCE ----------- ------ I/O SPACE MEMORY SPACE CONSTANT PTR INCREMENT PTR ; TERMINATE ON TC, INTERRUPT, SOURCE SYNCHRONIZE, INTERNAL REQUESTS, ; LOW PRIORITY RELATIVE TO CHANNEL 1, BYTE XFERS. AX, 0001011101010110B DX, D0CON DX, AX...
  • Page 328 Serial Communications Unit...
  • Page 330: Asynchronous Communications

    CHAPTER 11 SERIAL COMMUNICATIONS UNIT 11.1 INTRODUCTION The Serial Communications Unit is composed of two identical serial ports, or channels. Each se- rial port is independent of the other. This chapter describes the operation of a single serial port. The serial port implements several industry-standard asynchronous communications protocols, and it readily interfaces to many different processors over a standard serial interface.
  • Page 331: Rx Machine

    SERIAL COMMUNICATIONS UNIT Parity Stop Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 A1274-0A Figure 11-1. Typical 10-Bit Asynchronous Data Frame When discussing asynchronous communications, it makes sense to talk about the receive ma- chine (RX machine) and the transmit machine (TX machine) separately.
  • Page 332 SERIAL COMMUNICATIONS UNIT A1283-0A Figure 11-2. RX Machine 11-3...
  • Page 333: Tx Machine

    SERIAL COMMUNICATIONS UNIT The RX machine can detect several error conditions that may occur during reception: Parity errors — A parity error flag is set when the parity of the received data is incorrect. Framing errors — If a valid stop bit is not received when expected by the RX machine, a framing error flag is set.
  • Page 334 SERIAL COMMUNICATIONS UNIT A1284-0A Figure 11-3. TX Machine 11-5...
  • Page 335: Modes 1, 3 And 4

    SERIAL COMMUNICATIONS UNIT The Transmit machine can be disabled by an external source by using the Clear-to-Send feature. When the Clear-to-Send feature is enabled, the TX machine will not transmit until the CTS pin is asserted. The CTS pin is level sensitive. Asserting the CTS pin before a pending transmission for at least 1½...
  • Page 336: Mode 2

    SERIAL COMMUNICATIONS UNIT Parity TXD/ Start Stop Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 A1286-0A Figure 11-5. Mode 3 Waveform Start TXD/ Stop Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5...
  • Page 337: Synchronous Communications

    SERIAL COMMUNICATIONS UNIT At the end of the communication, the target slave switches back to Mode 2 and waits for another address. The parity feature cannot be used when implementing multiprocessor communications with Modes 2 and 3, as the ninth data bit is a control bit and cannot be used as the parity bit. 11.1.2 Synchronous Communications The synchronous mode (Mode 0) is useful primarily with shift register-based peripheral devices.
  • Page 338: Programming

    State RB7:0 Received Received data byte. Data NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 11-8. Serial Receive Buffer Register (SxRBUF) 11-9...
  • Page 339: Baud Rates

    Data byte to be transmitted. Data Field NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 11-9. Serial Transmit Buffer Register (SxTBUF) 11.2.1 Baud Rates The baud rate generator is composed of a 15-bit counter register (BxCNT) and a 15-bit compare register (BxCMP).
  • Page 340 NOTE: Writing to this register while the serial port is transmitting causes indeterminate operation. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 11-10. Baud Rate Counter Register (BxCNT) 11-11...
  • Page 341 SERIAL COMMUNICATIONS UNIT Register Name: Baud Rate Compare Register Register Mnemonic: BxCMP Register Function: Determines baud rate for the serial port. A1276-0A Reset Bit Name Function Mnemonic State ICLK Internal Selects the input clock: Clocking 0 = BCLK is input to baud clock. 1 = CPU clock is input to baud clock.
  • Page 342: Asynchronous Mode Programming

    SERIAL COMMUNICATIONS UNIT Due to internal synchronization requirements, the maximum input frequency to BCLK is one-half the CPU operating frequency. See “BCLK Pin Timings” on page 11-18 for more information. Ta- ble 11-1 shows the correct BxCMP values for common baud rates. Table 11-1.
  • Page 343: Modes 2 And 3 For Multiprocessor Communications

    SERIAL COMMUNICATIONS UNIT If the Clear-to-Send feature is used, set the CEN bit to enable it. If receptions are desired, set the REN bit to enable the RX machine. Note the TX machine need not be explicitly enabled. At this point, you will be able to transmit and receive in the mode specified. Now that the serial port is operating, you must correctly interpret its status.
  • Page 344 11-Bit Asynch Mode3 9-Bit Asynch Mode4 Reserved Reserved Reserved NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 11-13. Serial Port Control Register (SxCON) 11-15...
  • Page 345 NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 11-14. Serial Port Status Register (SxSTS) 11-16...
  • Page 346 Accessing SxSTS does not clear CTS. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 11-14. Serial Port Status Register (Continued) When either BREAK character is detected, an overrun error occurs (OE is set). SxRBUF will con- tain at least one null character.
  • Page 347: Programming In Mode 0

    SERIAL COMMUNICATIONS UNIT 11.2.3 Programming in Mode 0 Programming is much easier in Mode 0 than in the asynchronous modes. Configuring SxCON (Figure 11-13 on page 11-15) for Mode 0 requires only two steps: Program M2:0 with the correct combination for Mode 0. If the Clear-to-Send feature is desired, set the CEN bit.
  • Page 348 SERIAL COMMUNICATIONS UNIT The CPU samples BCLK on the rising edge of CLKOUT. The CLKOUT high time synchronizes the BCLK signal. On the falling edge of CLKOUT, the synchronized BCLK signal is presented to the baud timebase clock. CTS Resolved During CLKOUT High Time CLKOUT...
  • Page 349: Mode 0 Timings

    SERIAL COMMUNICATIONS UNIT BCLK is an asynchronous input. However, the pin does have setup and hold times, which guar- antee recognition at a specific CLKOUT. If the BCLK input signal has high and low times that are both at least 1½ CLKOUT periods, than synchronization to CLKOUT is not necessary. How- ever, when the BCLK signal has a high or a low time of less than 1½...
  • Page 350: Bclk As Baud Timebase Clock

    SERIAL COMMUNICATIONS UNIT 11.3.3.2 BCLK as Baud Timebase Clock BCLK does not run directly into the baud timebase clock, but is first synchronized to the CPU clock. BCLK causes the baud timebase clock to increment, but transitions on TXD and RXD (for transmissions) still occur relative to CLKOUT.
  • Page 351 SERIAL COMMUNICATIONS UNIT $mod186 name scu_async_example ; Example initialization code for the Serial Communications Unit. ; ASYNC_CHANNEL_SETUP sets up channel 0 as 9600 baud, full duplex, 7 data bits ; plus parity, with CTS# control. ; We assume serial port registers have been correctly defined and ;...
  • Page 352: Mode 0 Example

    SERIAL COMMUNICATIONS UNIT 11.5.2 Mode 0 Example Example 11-2 shows a sample Mode 0 application. $mod186 name example_SCU_mode_0 ;************************************************************** ; FUNCTION: This function transmits the user's data, user_data, serially ; over RXD1. TXD1 provides the transmit clock. The transmission frequency ;...
  • Page 353: Master/Slave Example

    SERIAL COMMUNICATIONS UNIT dx, P1CON ;Get state of port 1 controls ax, dx ax, 0feh ;make sure P1.0 is port dx, al dx, B1CMP ax, tran_freq ax, 8000h ;set internal clocking bit dx, ax ;Mode 0, 1 million bps dx, P2CON ;set Port 2.1 for TXD ax, 0ffh dx, al...
  • Page 354 SERIAL COMMUNICATIONS UNIT MASTER 186 Core Device Master Transmit Line Master Receive Line TXD RXD Port Port Port 186 Core 80C51 80C196 Device SLAVES A1273-0A Figure 11-18. Master/Slave Example Example 11-3 demonstrates how to implement a master/slave network in a typical system. The remaining three examples show the routines used in the implementation.
  • Page 355 SERIAL COMMUNICATIONS UNIT $mod186 name example_master_slave ;******************************************************************* ; FUNCTION: This function demonstrates how to implement the three ; master/slave routines (_slave_1, _select_slave, and _send_slave_command) ; in a typical setup. ; NOTE: It is assumed that the network is set up as shown in Figure 11-18, that the slave unit is running the _slave_1 code, and that the PCB is located in I/O space.
  • Page 356 SERIAL COMMUNICATIONS UNIT $mod186 name example_master_select_slave ;**************************************************************; select_slave ; FUNCTION: This function transmits a slave address, _slave_addr, over the ; serial network, with data bit 9 set to one. It then waits for the addressed ; slave to respond with its (slave) address. If this address does not match ;...
  • Page 357 SERIAL COMMUNICATIONS UNIT dx, S1STS ;clear any pending exceptions ax, dx dx, S1CON ;prepare to send address ax, 0083h ;d9=1, mode 3 dx, ax dx, S1TBUF ;select slave ax, _slave_addr ;get slave address dx, al ;send it dx, S1CON ax, 0023h ;set REN dx, ax ;enable receiver...
  • Page 358 SERIAL COMMUNICATIONS UNIT $mod186 name example_slave_1_routine ;**************************************************************; slave_1 ; FUNCTION: This function represents a slave unit connected to a multi- processor master/slave network. This slave responds to two commands: Flash the LEDs on the EVAL Board, and Disconnect from the Network. Other commands are easily added.
  • Page 359 SERIAL COMMUNICATIONS UNIT DisconnectMode: dx, S1STS ; clear any pending exceptions ax,dx dx, P1CON ; get state of port 1 controls ax, dx ax, 0f0h ; make sure P1.0:P1.3 is port dx, ax dx, P2CON ; set P2.1 for TXD1, P2.0for RXD1 ax, 0ffh dx, ax dx, P1LTCH...
  • Page 360 SERIAL COMMUNICATIONS UNIT al, FlashLEDs ; Flash LEDs command Wait_4_Cmd ; no: then ignore dx, P1LTCH ; yes: then flash LEDs 10 times cx, 20 ax, ax Send: dx, ax mov bx, 0ffffh Dly1: Dly1 Send short Wait_4_Cmd _slave_1 endp lib_80186 ends Example 11-5.
  • Page 361 SERIAL COMMUNICATIONS UNIT $mod186 name example_master_send_slave_command ;************************************************************************ send_slave_cmd ; FUNCTION: This function transmits a slave command, _slave_cmd, over the serial network to a previously addressed slave. ; SYNTAX: extern void far send_slave_cmd (int slave_cmd) ; INPUTS: _slave_cmd (command to send to addressed slave) ;...
  • Page 362 Watchdog Timer Unit...
  • Page 364: Using The Watchdog Timer As A System Watchdog

    CHAPTER 12 WATCHDOG TIMER UNIT System upsets can come from a variety of sources. Errant software can work its way into an end- less loop, waiting for an event that never occurs. An unanticipated radiation source can couple into improperly shielded circuitry. Not all sources of system upsets can be anticipated and guard- ed against.
  • Page 365 WATCHDOG TIMER UNIT Figure 12-2 shows the circuit necessary to reset the processor when a WDT timeout occurs. The power-on reset signal and the WDTOUT signals are ANDed together to produce the RESIN sig- nal for the processor. Internal Data Bus (F-BUS) 32-BIT Reload Value Protection And Control...
  • Page 366: Reloading The Watchdog Timer Down Counter

    WATCHDOG TIMER UNIT Figure 12-3(b) shows the circuit necessary to generate an NMI from WDTOUT. NMI is edge sen- sitive and level latched. The inverter is needed to prevent an NMI immediately upon reset. When using interrupts to recover from a system upset, pay close attention to “Using the Watch- dog Timer as a General-Purpose Timer”...
  • Page 367: Watchdog Timer Reload Value

    WATCHDOG TIMER UNIT 12.2.2 Watchdog Timer Reload Value The Watchdog Timer Reload Value is controlled by the WDTRLDL and WDTRLDH registers in the Peripheral Control Block. These two registers make up the 32-bit reload value. The Watchdog Timer Reload Value cannot be modified after the Watchdog Timer is reloaded us- ing the reload instruction sequence.
  • Page 368: Initialization

    WATCHDOG TIMER UNIT wdt_data segment wdt_key 0AAH, 055H wdt_data ends pcb_image segment ;image of PCB WDTCLR XXXXH ;replace “XXXX” with appropriate ;offset from PCB+0. WDTCLR pcb_image ends wdt_code segment assume cs:wdt_code ax, seg wdt_key ds, ax si, offset wdt_key ;DS:SI = address of WDT reset value ax, seg WDTCLR es, ax di, offset WDTCLR...
  • Page 369: Using The Watchdog Timer As A General-Purpose Timer

    WATCHDOG TIMER UNIT 12.3 USING THE WATCHDOG TIMER AS A GENERAL-PURPOSE TIMER Systems that do not require a watchdog timer can program the Watchdog Timer Unit to function as a general-purpose timer. In reality, it is a lack of programming that allows the Watchdog Timer Unit to perform general-purpose timer tasks.
  • Page 370 WATCHDOG TIMER UNIT A LOCKed instruction sequence that is similar to the reload sequence disables the Watchdog Timer. The Watchdog Timer Disable (WDTDIS) Register expects a sequence of two bytes, which must be written by a single LOCKed instruction. The first byte must be 55H and the second must be 0AAH (the reverse of the reload sequence).
  • Page 371: Watchdog Timer Registers

    WATCHDOG TIMER UNIT wdt_data segment wdt_off 055H, 0AAH wdt_data ends pcb_image segment;image of PCB WDTDIS XXXXH ;replace “XXXX” with appropriate ;offset from PCB+0. WDTDIS pcb_image ends wdt_code segment assume cs:wdt_code ax, seg wdt_off ds, ax si, offset wdt_off ;DS:SI = address of disable ;value for the WDT ax, seg WDTDIS es, ax...
  • Page 372 WATCHDOG TIMER UNIT Register Name: Watchdog Timer Reload Value (High) Register Mnemonic: WDTRLDH Register Function: Contains the upper 16 bits of the Watchdog Timer Reload Value. A1308-0A Reset Bit Name Function Mnemonic State WR31:16 Watchdog 0000H WR31:16 are the high-order bits of the Timer Reload Watchdog Timer Reload Value.
  • Page 373 WATCHDOG TIMER UNIT Register Name: Watchdog Timer Reload Value (Low) Register Mnemonic: WDTRLDL Register Function: Contains the lower 16 bits of the Watchdog Timer Reload Value. A1309-0A Reset Bit Name Function Mnemonic State WR15:0 Watchdog FFFFH WR15:0 are the low-order bits of the Watchdog Timer Reload Timer Reload Value.
  • Page 374 WATCHDOG TIMER UNIT Register Name: Watchdog Timer Count Value (High) Register Mnemonic: WDTCNTH Register Function: Contains the upper 16 bits of the Watchdog Timer Count Value. A1306-0A Reset Bit Name Function Mnemonic State WC31:16 Watchdog 0000H WC31:16 are the high-order bits of the Timer Reload Watchdog Timer Counter Value.
  • Page 375: Initialization Example

    WATCHDOG TIMER UNIT Register Name: Watchdog Timer Count Value (Low) Register Mnemonic: WDTCNTL Register Function: Contains the lower 16 bits of the Watchdog Timer Count Value. A1307-0A Reset Bit Name Function Mnemonic State WC15:0 Watchdog FFFFH WC15:0 are the low-order bits of the Watchdog Timer Reload Timer Counter Value.
  • Page 376 WATCHDOG TIMER UNIT wdt_data segment wdt_key 0AAH, 055H wdt_data ends ; The following code must be executed within the first 64K clock cycles. boot_code segment assume cs:boot_code ; For this example, we want a delay of 2 seconds for the Watchdog ;...
  • Page 378 Input/Output Ports...
  • Page 380: Bidirectional Port

    I/O ports. Many of the on-chip peripheral pin functions are multiplexed with an I/O port. If a particular peripheral pin function is unnecessary in an applica- tion, that pin can be used for I/O. The 80C186EC/80C188EC has three types of ports: bidirection- al, output-only and open-drain bidirectional.
  • Page 381 INPUT/OUTPUT PORTS From Integrated Port/Peripheral Peripheral Data Multiplexer Read Port Data latch Output Driver Write Port Data Latch Port Data Latch Read Port Pin State SYNC Read Port Direction Control Internal Data Bus (F-Bus) Write Port Direction Port Direction Latch Read Port Direction Write Port...
  • Page 382: Output Port

    INPUT/OUTPUT PORTS 13.1.2 Output Port Figure 13-2 shows the internal construction of an output port pin. An internal connection perma- nently enables the three-state output driver. The Port Control latch selects the source of data for the pin, which can be either the on-chip peripheral or the Port Data latch. The Port Direction bit has no effect on an output-only pin;...
  • Page 383 INPUT/OUTPUT PORTS From Integrated Peripheral Output Driver Read Port (Permenantly Disabled) Data latch Write Port Data Latch Port Data Latch Read Port Pin State SYNC Read Port Direction Control Internal Data Bus (F-Bus) Write Port Direction Port Direction Latch Read Port Direction Write Port Control...
  • Page 384 INPUT/OUTPUT PORTS From Port Direction Latch Read Port Data Latch Internal Data Bus Port Data Latch Write Port Data Latch SYNC Read Port Pin State From Port Control Latch A1249-0A Figure 13-3. Simplified Logic Diagram of an Open-Drain Bidirectional Port 13-5...
  • Page 385: Port 1 Organization

    INPUT/OUTPUT PORTS 13.1.4.1 Port 1 Organization Port 1 consists of eight output-only port pins. The Port 1 pins are multiplexed with the general- purpose chip-selects (GCS7:0). Table 13-1 shows the multiplexing options for Port 1. Table 13-1. Port 1 Multiplexing Options Pin Name Peripheral Function Port Function...
  • Page 386: Port 3 Organization

    INPUT/OUTPUT PORTS 13.1.4.3 Port 3 Organization Port 3 consists of six pins: four output-only pins and two open-drain bidirectional pins. The four output-only port pins are multiplexed with DMA and serial communications interrupt requests. The two open-drain bidirectional pins are not multiplexed with a peripheral function. The multi- plexing options for Port 3 are shown in Table 13-3.
  • Page 387: Port Direction Register

    NOTE: PC7 and PC6 do not exist for Port 3. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 13-4. Port Control Register (PxCON) 13.2.2 Port Direction Register...
  • Page 388: Port Data Latch Register

    NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 13-5. Port Direction Register (PxDIR) 13.2.3 Port Data Latch Register The Port Data Latch Register (Figure 13-6) holds the value to be driven on an output or bidirec- tional pin.
  • Page 389: Port Pin State Register

    NOTE: PL7 and PL6 do not exist for Port 3. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be writ- ten to a logic zero to ensure compatibility with future Intel products. Figure 13-6. Port Data Latch Register (PxLTCH) 13.2.4 Port Pin State Register...
  • Page 390: Initializing The I/O Ports

    NOTE: PP7 and PP6 do not exist for Port 3. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 13-7. Port Pin State Register (PxPIN) 13.2.5 Initializing the I/O Ports...
  • Page 391: Programming Example

    INPUT/OUTPUT PORTS 13.3 PROGRAMMING EXAMPLE Example 13-1 shows a typical ASM86 routine to configure the I/O ports. GCS7 through GCS4 are routed to the pins, while P1.0 through P1.4 are used as output ports. The binary value 0101 is written to P1.0 through P1.3. The states of pins P3.5 and P3.4 are read and stored in the AL reg- ister.
  • Page 392 Math Coprocessing...
  • Page 394: Availability Of Math Coprocessing

    CHAPTER 14 MATH COPROCESSING The 80C186 Modular Core Family meets the need for a general-purpose embedded microproces- sor. In most data control applications, efficient data movement and control instructions are fore- most and arithmetic performed on the data is simple. However, some applications do require more powerful arithmetic instructions and more complex data types than those provided by the 80C186 Modular Core.
  • Page 395: The 80C187 Math Coprocessor

    MATH COPROCESSING 14.3 THE 80C187 MATH COPROCESSOR The 80C187’s high performance is due to its 80-bit internal architecture. It contains three units: a Floating Point Unit, a Data Interface and Control Unit and a Bus Control Logic Unit. The foun- dation of the Floating Point Unit is an 8-element register file, which can be used either as indi- vidually addressable registers or as a register stack.
  • Page 396: Data Transfer Instructions

    MATH COPROCESSING 14.3.1.1 Data Transfer Instructions Data transfer instructions move operands between elements of the 80C187 register stack or be- tween stack top and memory. Instructions can convert any data type to temporary real and load it onto the stack in a single operation. Conversely, instructions can convert a temporary real oper- and on the stack to any data type and store it to memory in a single operation.
  • Page 397 MATH COPROCESSING Available data types include temporary real, long real, short real, short integer and word integer. The 80C187 performs automatic type conversion to temporary real. Table 14-2. 80C187 Arithmetic Instructions Addition Division FADD Add real FDIV Divide real FADDP Add real and pop FDIVP Divide real and pop...
  • Page 398 MATH COPROCESSING 14.3.1.3 Comparison Instructions Each comparison instruction (see Table 14-3) analyzes the stack top element, often in relationship to another operand. Then it reports the result in the Status Word condition code. The basic oper- ations are compare, test (compare with zero) and examine (report tag, sign and normalization). Table 14-3.
  • Page 399 MATH COPROCESSING 14.3.1.5 Constant Instructions Each constant instruction (see Table 14-5) loads a commonly used constant onto the stack. The values have full 80-bit precision and are accurate to about 19 decimal digits. Since a temporary real constant occupies 10 memory bytes, the constant instructions, only 2 bytes long, save mem- ory space.
  • Page 400 MATH COPROCESSING 14.3.2 80C187 Data Types The microprocessor/math coprocessor combination supports seven data types: • Word Integer — A signed 16-bit numeric value. All operations assume a 2’s complement representation. • Short Integer — A signed 32-bit numeric value (double word). All operations assume a 2’s complement representation.
  • Page 401 MATH COPROCESSING Increasing Significance Word (Two's Complement) Magnitude Integer Short (Two's Complement) Magnitude Integer (Two's Long Magnitude Complement) Integer Magnitude Packed 10 d 9 Decimal Short Biased Significand Real Exponent Long Biased Significand Exponent Real Temporary Biased Significand Exponent Real 64 63 NOTES: S = Sign bit (0 = positive, 1 = negative)
  • Page 402 MATH COPROCESSING Latch External Oscillator AD15:0 CLKOUT 80C187 80C186 Modular Core RESET RESOUT NPWR NPRD BUSY BUSY ERROR ERROR PEREQ PEREQ NPS1 NPS2 D15:0 A1254-01 Figure 14-2. 80C186 Modular Core Family/80C187 System Configuration 14-9...
  • Page 403 MATH COPROCESSING 14.4.1 Clocking the 80C187 The microprocessor and math coprocessor operate asynchronously, and their clock rates may dif- fer. The 80C187 has a CKM pin that determines whether it uses the input clock directly or divided by two. Direct clocking works up to 12.5 MHz, which makes it convenient to feed the clock input from the microprocessor’s CLKOUT pin.
  • Page 404 MATH COPROCESSING Bus cycles involving the 80C187 Math Coprocessor behave exactly like other I/O bus cycles with respect to the processor’s control pins. See “System Design Tips” for information on integrating the 80C187 into the overall system. 14.4.3 System Design Tips All 80C187 operations require that bus ready be asserted.
  • Page 405 MATH COPROCESSING Latch External A15:0 Oscillator Buffer D15:8 AD15:0 T OE CLKOUT 80C187 80C186 Modular Core RESET Buffer RESOUT D7:0 NPWR NPRD BUSY BUSY ERROR ERROR PEREQ PEREQ NPS1 NPS2 DT/R D15:0 A1255-01 Figure 14-3. 80C187 Configuration with a Partially Buffered Bus 14-12...
  • Page 406 MATH COPROCESSING 14.4.4 Exception Trapping The 80C187 detects six error conditions that can occur during instruction execution. The 80C187 can apply default fix-ups or signal exceptions to the microprocessor’s ERROR pin. The processor tests ERROR at the beginning of numerics instructions, so it traps an exception on the next at- tempted numerics instruction after it occurs.
  • Page 407 MATH COPROCESSING 80C186 Modular Core ERROR RESOUT CS x INT x Latch BUSY PEREQ A19:A16 AD15:0 CLKOUT D15:0 D15:0 CMD1 NPWR A19:0 CMD0 NPRD 80C187 NPS1 PEREQ BUSY NPS2 ERROR RESET A1256-01 Figure 14-4. 80C187 Exception Trapping via Processor Interrupt Pin 14-14...
  • Page 408 MATH COPROCESSING $mod186 name example_80C187_init ;FUNCTION: This function initializes the 80C187 numerics coprocessor. ;SYNTAX: extern unsigned char far 187_init(void); ;INPUTS: None ;OUTPUTS: unsigned char - 0000h -> False -> coprocessor not initialized ffffh -> True -> coprocessor initialized ;NOTE: Parameters are passed on the stack as required by high-level languages.
  • Page 409 The results of the computation are the coordinates x and y expressed as 32-bit reals. ;NOTES: This routine is coded for Intel ASM86. It is not set up as an HLL-callable routine. This code assumes that the 80C187 has already been initialized.
  • Page 410 ONCE Mode...
  • Page 412 CHAPTER 15 ONCE MODE ONCE (pronounced “ahnce”) Mode provides the ability to three-state all output, bidirectional, or weakly held high/low pins except OSCOUT. To allow device operation with a crystal network, OSCOUT does not three-state. ONCE Mode electrically isolates the device from the rest of the board logic. This isolation allows a bed-of-nails tester to drive the device pins directly for more accurate and thorough testing.
  • Page 414 80C186 Instruction Set Additions and Extensions...
  • Page 416 APPENDIX A 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS The 80C186 Modular Core family instruction set differs from the original 8086/8088 instruction set in two ways. First, several instructions that were not available in the 8086/8088 instruction set have been added. Second, several 8086/8088 instructions have been enhanced for the 80C186 Modular Core family instruction set.
  • Page 417 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A.1.2 String Instructions INS source_string, port INS (in string) performs block input from an I/O port to memory. The port address is placed in the DX register. The memory address is placed in the DI register. This instruction uses the ES segment register (which cannot be overridden).
  • Page 418 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS The following listing gives the formal definition of the ENTER instruction for all cases. LEVEL denotes the value of the second operand. Push BP Set a temporary value FRAME_PTR: = SP If LEVEL > 0 then Repeat (LEVEL - 1) times: BP:=BP - 2 Push the word pointed to by BP...
  • Page 419 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Main Program (Lexical Level 1) Procedure A (Lexical Level 2) Procedure B (Lexical Level 3) Procedure C (Lexical Level 3) Procedure D (Lexical Level 4) A1001-0A Figure A-2. Variable Access in Nested Procedures The first ENTER, executed in the Main Program, allocates dynamic storage space for Main, but no pointers are copied.
  • Page 420 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Old BP Display A BPA* Dynamic Storage A *BPA = BP Value for Procedure A A1003-0A Figure A-4. Stack Frame for Procedure A at Level 2 After Procedure A calls Procedure B, ENTER creates the display for Procedure B. The first word of the display points to the previous value of BP (BPA).
  • Page 421 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Old BP Display B Dynamic Storage B A1004-0A Figure A-5. Stack Frame for Procedure B at Level 3 Called from A...
  • Page 422 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Old BP Display C Dynamic Storage C A1005-0A Figure A-6. Stack Frame for Procedure C at Level 3 Called from B LEAVE LEAVE reverses the action of the most recent ENTER instruction. It collapses the last stack frame created.
  • Page 423 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS BOUND register, address BOUND verifies that the signed value in the specified register lies within specified limits. If the value does not lie within the bounds, an array bounds exception (type 5) occurs. BOUND is useful for checking array bounds before attempting to access an array element.
  • Page 424 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A.2.2 Arithmetic Instructions IMUL destination, source, data IMUL (integer immediate multiply, signed) allows a value to be multiplied by an immediate op- erand. IMUL requires three operands. The first, destination, is the register where the result will be placed.
  • Page 425 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A.2.3.2 Rotate Instructions ROL destination, count ROL (immediate rotate left) rotates the destination byte or word left by an immediate value. ROL has two operands. The first, destination, is the effective address to be rotated. The second, count, is an immediate byte value representing the number of rotations to be made.
  • Page 426 Input Synchronization...
  • Page 428 APPENDIX B INPUT SYNCHRONIZATION Many input signals to an embedded processor are asynchronous. Asynchronous signals do not re- quire a specified setup or hold time to ensure the device does not incur a failure. However, asyn- chronous setup and hold times are specified in the data sheet to ensure recognition. Associated with each of these inputs is a synchronizing circuit (see Figure B-1) that samples the asynchro- nous signal and synchronizes it to the internal operating clock.
  • Page 429 As the sampling window gets smaller, the number of times an asynchro- nous transition occurs during the sampling window drops. ASYNCHRONOUS PINS The 80C186EC/80C188EC inputs that use the two-stage synchronization circuit are T0IN, T1IN, NMI, TEST/BUSY, INT7:0, HOLD, all port pins used as inputs, and DRQ3:0.
  • Page 430 Instruction Set Descriptions...
  • Page 432 APPENDIX C INSTRUCTION SET DESCRIPTIONS This appendix provides reference information for the 80C186 Modular Core family instruction set. Tables C-1 through C-3 define the variables used in Table C-4, which lists the instructions with their descriptions and operations. Table C-1. Instruction Format Variables Variable Description dest...
  • Page 433 INSTRUCTION SET DESCRIPTIONS Table C-2. Instruction Operands Operand Description An 8- or 16-bit general register. reg16 An 16-bit general register. seg-reg A segment register. accum Register AX or AL immed A constant in the range 0–FFFFH. immed8 A constant in the range 0–FFH. An 8- or 16-bit memory location.
  • Page 434 INSTRUCTION SET DESCRIPTIONS Table C-3. Flag Bit Functions Name Function Auxiliary Flag: Set on carry from or borrow to the low order four bits of AL; cleared otherwise. Carry Flag: Set on high-order bit carry or borrow; cleared otherwise. Direction Flag: Causes string instructions to auto decrement the appropriate index register when set.
  • Page 435 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set Flags Name Description Operation Affected ü ASCII Adjust for Addition: ü ((AL) and 0FH) > 9 or (AF) = 1 then DF – Changes the contents of register AL to (AL) ← (AL) + 6 IF –...
  • Page 436 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü ASCII Adjust for Subtraction: ü ((AL) and 0FH) > 9 or (AF) = 1 then DF – Corrects the result of a previous (AL) ← (AL) – 6 IF –...
  • Page 437 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü (dest) ← (dest) + (src) Addition: ü ADD dest , src DF – Sums two operands, which may be IF – ü bytes or words, replaces the ü...
  • Page 438 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected BOUND Detect Value Out of Range: AF – ((dest) < (src) or (dest) > ((src) + 2) CF – BOUND dest , src then DF – Provides array bounds checking in (SP) ←...
  • Page 439 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Convert Byte to Word: AF – (AL) < 80H CF – then DF – Extends the sign of the byte in register (AH) ← 0 IF – AL throughout register AH.
  • Page 440 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (IF) ← 0 Clear Interrupt-enable Flag: AF – CF – DF – ü Zeroes the interrupt-enable flag (IF). When the interrupt-enable flag is OF – cleared, the 8086 and 8088 do not PF –...
  • Page 441 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü Compare: (dest) – (src) ü CMP dest , src DF – Subtracts the source from the desti- IF – ü nation, which may be bytes or words, ü...
  • Page 442 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Convert Word to Doubleword: AF – (AX) < 8000H CF – then DF – Extends the sign of the word in register (DX) ← 0 IF – AX throughout register DX.
  • Page 443 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü (dest) ← (dest) – 1 Decrement: CF – DEC dest DF – Subtracts one from the destination IF – ü operand. The operand may be a byte ü...
  • Page 444 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Divide: When Source Operand is a Byte: AF ? CF ? (temp) ← (byte-src) DIV src DF – Performs an unsigned division of the IF – (temp) / (AX) > FFH accumulator (and its extension) by the OF ? then (type 0 interrupt is generated)
  • Page 445 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (SP) ← (SP) – 2 ENTER Procedure Entry: AF – ((SP) + 1:(SP)) ← (BP) CF – ENTER locals, levels (FP) ← (SP) DF – Executes the calling sequence for a IF –...
  • Page 446 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Halt: None AF – CF – DF – Causes the CPU to enter the halt IF – state. The processor leaves the halt OF – state upon activation of the RESET PF –...
  • Page 447 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected IDIV Integer Divide: When Source Operand is a Byte: AF ? CF ? (temp) ← (byte-src) IDIV src DF – Performs a signed division of the IF – (temp) / (AX) >...
  • Page 448 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected IMUL Integer Multiply: When Source Operand is a Byte: AF ? ü (AX) ← (byte-src) × (AL) IMUL src DF – Performs a signed multiplication of the IF –...
  • Page 449 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü (dest) ← (dest) + 1 Increment: CF – INC dest DF – Adds one to the destination operand. IF – ü The operand may be byte or a word ü...
  • Page 450 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (SP) ← (SP) – 2 Interrupt: AF – ((SP) + 1:(SP)) ← FLAGS CF – INT interrupt-type (IF) ← 0 DF – ü Activates the interrupt procedure (TF) ←...
  • Page 451 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected INTO Interrupt on Overflow: AF – (OF) = 1 CF – INTO then DF – Generates a software interrupt if the (SP) ← (SP) – 2 IF – overflow flag (OF) is set;...
  • Page 452 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Jump on Above or Equal: AF – Jump on Not Below: (CF) = 0 CF – then DF – JAE disp8 (IP) ← (IP) + disp8 (sign-ext to 16 bits) IF –...
  • Page 453 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected JCXZ Jump if CX Zero: AF – (CX) = 0 CF – JCXZ disp8 then DF – Transfers control to the target location (IP) ← (IP) + disp8 (sign-ext to 16 bits) IF –...
  • Page 454 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Jump on Less Than: AF – (SF) ≠ (OF) JNGE Jump on Not Greater Than or Equal: CF – then DF – JL disp8 (IP) ← (IP) + disp8 (sign-ext to 16 bits) IF –...
  • Page 455 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Jump on Not Equal: AF – Jump on Not Zero: (ZF) = 0 CF – then DF – JNE disp8 (IP) ← (IP) + disp8 (sign-ext to 16 bits) IF –...
  • Page 456 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Jump on Overflow: AF – (OF) = 1 CF – JO disp8 then DF – Transfers control to the target location (IP) ← (IP) + disp8 (sign-ext to 16 bits) IF –...
  • Page 457 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (dest) ← (EA) Load Pointer Using DS: AF – (DS) ← (EA + 2) CF – LDS dest, src DF – Transfers a 32-bit pointer variable from IF –...
  • Page 458 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (dest) ← (EA) Load Pointer Using ES: AF – (ES) ← (EA + 2) CF – LES dest, src DF – Transfers a 32-bit pointer variable from IF –...
  • Page 459 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected LODS Load String (Byte or Word): When Source Operand is a Byte: AF – CF – (AL) ← (src-string) LODS src-string DF – Transfers the byte or word string IF –...
  • Page 460 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (CX) ← (CX) – 1 LOOPNE Loop While Not Equal: AF – LOOPNZ Loop While Not Zero: CF – (ZF) = 0 and (CX) ≠ 0 DF – LOOPNE disp8 then IF –...
  • Page 461 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (dest-string) ← (src-string) MOVS Move String: AF – CF – MOVS dest-string, src-string DF – Transfers a byte or a word from the IF – source string (addressed by SI) to the OF –...
  • Page 462 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü Negate: When Source Operand is a Byte: ü (dest) ← FFH – (dest) NEG dest DF – (dest) ← (dest) + 1 (affecting flags) Subtracts the destination operand, IF –...
  • Page 463 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (dest) ← (dest) or (src) Logical OR: AF ? ü (CF) ← 0 OR dest,src (OF) ← 0 DF – Performs the logical "inclusive or" of IF – ü...
  • Page 464 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (dst) ← (src) OUTS Out String: AF – CF – OUTS port, src_string DF – Performs block output from memory to IF – an I/O port. The port address is placed OF –...
  • Page 465 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (DI) ← ((SP) + 1:(SP)) POPA Pop All: AF – (SP) ← (SP) + 2 CF – POPA (SI) ← ((SP) + 1:(SP)) DF – Pops all data, pointer, and index (SP) ←...
  • Page 466 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected temp ← (SP) PUSHA Push All: AF – (SP) ← (SP) – 2 CF – PUSHA ((SP) + 1:(SP)) ← (AX) DF – Pushes all data, pointer, and index (SP) ←...
  • Page 467 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (temp) ← count Rotate Through Carry Left: AF – ü do while (temp) ≠ 0 RCL dest, count (tmpcf) ← (CF) DF – Rotates the bits in the byte or word (CF) ←...
  • Page 468 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected do while (CX) ≠ 0 Repeat: AF – REPE Repeat While Equal: service pending interrupts (if any) CF – REPZ Repeat While Zero: execute primitive string DF – REPNE Repeat While Not Equal: Operation in succeeding byte...
  • Page 469 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (IP) ← ((SP) = 1:(SP)) Return: AF – (SP) ← (SP) + 2 CF – RET optional-pop-value DF – Transfers control from a procedure inter-segment IF – back to the instruction following the then OF –...
  • Page 470 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (temp) ← count Rotate Right: AF – ü do while (temp) ≠ 0 ROR dest, count (CF) ← low-order bit of (dest) DF – Operates similar to ROL except that (dest) ←...
  • Page 471 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (temp) ← count Shift Logical Left: AF ? ü do while (temp) ≠ 0 Shift Arithmetic Left: (CF) ← high-order bit of (dest) DF – SHL dest, count (dest) ←...
  • Page 472 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü Subtract With Borrow: ü (CF) = 1 SBB dest, src then DF – Subtracts the source from the desti- (dest) = (dest) – (src) – 1 IF –...
  • Page 473 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü SCAS Scan String: When Source Operand is a Byte: ü SCAS dest-string (AL) – (byte-string) DF – Subtracts the destination string IF – (DF) = 0 ü...
  • Page 474 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (temp) ← count Shift Logical Right: AF ? ü do while (temp) ≠ 0 SHR dest, src (CF) ← low-order bit of (dest) DF – Shifts the bits in the destination (dest) ←...
  • Page 475 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (IF) ← 1 Set Interrupt-enable Flag: AF – CF – DF – ü Sets IF to 1, enabling processor recognition of maskable interrupt OF – requests appearing on the INTR line. PF –...
  • Page 476 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü (dest) ← (dest) – (src) Subtract: ü SUB dest, src DF – The source operand is subtracted from IF – ü the destination operand, and the result ü...
  • Page 477 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected WAIT Wait: None AF – CF – WAIT DF – Causes the CPU to enter the wait state IF – while its test line is not active. OF –...
  • Page 478 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected AL ← ((BX) + (AL)) XLAT Translate: AF – CF – XLAT translate-table DF – Replaces a byte in the AL register with IF – a byte from a 256-byte, user-coded OF –...
  • Page 480 Instruction Set Opcodes and Clock Cycles...
  • Page 482 APPENDIX D INSTRUCTION SET OPCODES AND CLOCK CYCLES This appendix provides reference information for the 80C186 Modular Core family instruction set. Table D-1 defines the variables used in Table D-2, which lists the instructions with their for- mats and execution times. Table D-3 is a guide for decoding machine instructions. Table D-4 is a guide for encoding instruction mnemonics, and Table D-5 defines Table D-4 abbreviations.
  • Page 483 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary Function Format Clocks Notes DATA TRANSFER INSTRUCTIONS MOV = Move register to register/memory 1 0 0 0 1 0 0 w mod reg r/m 2/12 register/memory to register 1 0 0 0 1 0 1 w mod reg r/m immediate to register/memory 1 1 0 0 0 1 1 w...
  • Page 484 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes DATA TRANSFER INSTRUCTIONS (Continued) LEA = Load EA to register 1 0 0 0 1 1 0 1 mod reg r/m LDS = Load pointer to DS 1 1 0 0 0 1 0 1 mod reg r/m (mod ?11)
  • Page 485 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes ARITHMETIC INSTRUCTIONS (Continued) SUB = Subtract reg/memory with register to either 0 0 1 0 1 0 d w mod reg r/m 3/10 immediate from register/memory 1 0 0 0 0 0 s w mod 101 r/m data...
  • Page 486 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes ARITHMETIC INSTRUCTIONS (Continued) AAM = ASCII adjust for multiply 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 DIV = Divide (unsigned) 1 1 1 1 0 1 1 w mod 110 r/m...
  • Page 487 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes BIT MANIPULATION INSTRUCTIONS (Continued) TEST= And function to flags, no result register/memory and register 1 0 0 0 0 1 0 w mod reg r/m 3/10 immediate data and register/memory 1 1 1 1 0 1 1 w...
  • Page 488 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes PROGRAM TRANSFER INSTRUCTIONS Conditional Transfers — jump if: JE/JZ= equal/zero 0 1 1 1 0 1 0 0 disp 4/13 JL/JNGE = less/not greater or equal 0 1 1 1 1 1 0 0 disp 4/13...
  • Page 489 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes PROGRAM TRANSFER INSTRUCTIONS (Continued) RET = Return from procedure within segment 1 1 0 0 0 0 1 1 within segment adding immed to SP 1 1 0 0 0 0 1 0 data-low data-high...
  • Page 490 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes PROCESSOR CONTROL INSTRUCTIONS CLC = Clear carry 1 1 1 1 1 0 0 0 CMC = Complement carry 1 1 1 1 0 1 0 1 STC = Set carry 1 1 1 1 1 0 0 1 CLD = Clear direction...
  • Page 491 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Bytes 3–6 ASM-86 Instruction Format Binary 0000 1001 mod reg r/m (disp-lo),(disp-hi) reg16/mem16,reg16 0000 1010 mod reg r/m (disp-lo),(disp-hi) reg8,reg8/mem8 0000 1011 mod reg r/m (disp-lo),(disp-hi) reg16,reg16/mem16 0000 1100...
  • Page 492 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Bytes 3–6 ASM-86 Instruction Format Binary 0010 1110 (segment override prefix) 0010 1111 0011 0000 mod reg r/m (disp-lo),(disp-hi) reg8/mem8,reg8 0011 0001 mod reg r/m (disp-lo),(disp-hi) reg16/mem16,reg16 0011 0010...
  • Page 493 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Bytes 3–6 ASM-86 Instruction Format Binary 0101 0011 push 0101 0100 push 0101 0101 push 0101 0110 push 0101 0111 push 0101 1000 0101 1001 0101 1010 0101 1011...
  • Page 494 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Bytes 3–6 ASM-86 Instruction Format Binary 0111 1110 IP-inc-8 jle/jng short-label 0111 1111 IP-inc-8 jnle/jg short-label 1000 0000 mod 000 r/m (disp-lo),(disp-hi), data-8 reg8/mem8,immed8 mod 001 r/m (disp-lo),(disp-hi), data-8...
  • Page 495 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Bytes 3–6 ASM-86 Instruction Format Binary 1000 0111 mod reg r/m (disp-lo),(disp-hi) xchg reg16,reg16/mem16 1000 0100 mod reg r/m (disp-lo),(disp-hi) reg8/mem8,reg8 1000 1001 mod reg r/m (disp-lo),(disp-hi) reg16/mem16,reg16...
  • Page 496 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Bytes 3–6 ASM-86 Instruction Format Binary 1010 1010 stos dest-str8 1010 1011 stos dest-str16 1010 1100 lods src-str8 1010 1101 lods src-str16 1010 1110 scas dest-str8 1010 1111...
  • Page 497 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Bytes 3–6 ASM-86 Instruction Format Binary mod 111 r/m data-8 reg16/mem16, immed8 1100 0010 data-lo data-hi immed16 (intrasegment) 1100 0011 (intrasegment) 1100 0100 mod reg r/m (disp-lo),(disp-hi) reg16,mem16...
  • Page 498 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Bytes 3–6 ASM-86 Instruction Format Binary 1101 0001 mod 000 r/m (disp-lo),(disp-hi) reg16/mem16,1 mod 001 r/m (disp-lo),(disp-hi) reg16/mem16,1 1101 0001 mod 010 r/m (disp-lo),(disp-hi) reg16/mem16,1 mod 011 r/m...
  • Page 499 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Bytes 3–6 ASM-86 Instruction Format Binary 1110 0001 IP-inc-8 loope/loopz short-label 1110 0010 IP-inc-8 loop short-label 1110 0011 IP-inc-8 jcxz short-label 1110 0100 data-8 AL,immed8 1110 0101...
  • Page 500 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Bytes 3–6 ASM-86 Instruction Format Binary 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 mod 000 r/m (disp-lo),(disp-hi) mem16 mod 001 r/m...
  • Page 501 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4. Mnemonic Encoding Matrix (Left Half) PUSH b,f,r/m w,f,r/m b,t,r/m w,t,r/m b,ia w,ia PUSH b,f,r/m w,f,r/m b,t,r/m w,t,r/m b,f,r/m w,f,r/m b,t,r/m w,t,r/m b,f,r/m w,f,r/m b,t,r/m w,t,r/m PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSHA POPA...
  • Page 502 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4. Mnemonic Encoding Matrix (Right Half) PUSH b,f,r/m w,f,r/m b,t,r/m w,t,r/m PUSH b,f,r/m w,f,r/m b,t,r/m w,t,r/m b,f,r/m w,f,r/m b,t,r/m w,t,r/m b,f,r/m w,f,r/m b,t,r/m w,t,r/m PUSH IMUL PUSH IMUL OUTS OUTS JNP/ JNL/ JLE/ JNLE/ JNGE b,f,r/m...
  • Page 503 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-5. Abbreviations for Mnemonic Encoding Matrix Abbr Definition Abbr Definition Abbr Definition Abbr Definition byte operation immediate to accumulator memory to CPU register direct indirect EA is second byte variable from CPU register immediate byte, sign extended short intrasegment word operation...
  • Page 504 Index...
  • Page 506 INDEX 80C187 Math Coprocessor, 14-2–14-8 programming, 8-20–8-35 accessing, 14-10–14-11 sequence, 8-21–8-23 arithmetic instructions, 14-3–14-4 registers bus cycles, 14-11 addressing, 8-21 clocking, 14-10 reading, 8-34 code examples, 14-13–14-16 selecting Automatic EOI Mode, 8-26 comparison instructions, 14-5 selecting cascade mode, 8-24 constant instructions, 14-6 selecting edge- or level-triggered interrupts, data transfer instructions, 14-3 8-24...
  • Page 507 INDEX AH register, 2-5 and chip-selects, 6-4 AL register, 2-5, 2-18, 2-23 and external 8259A devices, 8-45 ApBUILDER files, obtaining from BBS, 1-6 and ICU, 8-44 Application BBS, 1-5 operation, 3-7–3-20 Architecture priorities, 3-46–3-47, 7-2 CPU block diagram, 2-2 read cycles, 3-20–3-22 device feature comparisons, 1-2 refresh cycles, 3-22–3-23, 7-4, 7-5 family introduction, 1-1...
  • Page 508 INDEX registers, 6-5–6-15 Data segment, 2-5 system diagram, 6-16 Data sheets, obtaining from BBS, 1-6 See also Chip selects Data transfers, 3-1–3-6 Chip-selects instructions, 2-18 activating, 6-4 PCB considerations, 4-5 and 80C187 interface, 6-14, 14-11 PSW flag storage formats, 2-19 and bus hold protocol, 6-15 See also Bus cycles and DMA acknowledge signal, 10-30...
  • Page 509 INDEX synchronization, 10-23 Emulation mode, 15-1 transfer count, 10-24–10-25 End-of-Interrupt (EOI) command, 8-32 programming, pointers, 10-15–10-19 and polling, 8-35 requests, 10-3 automatic EOI, 8-13 external, 10-4 issuing in a cascaded system, 8-17 internal, 10-6–10-7 non-specific EOI, 8-13, 8-33 multiplexer, 10-11 rotate in automatic EOI mode, 8-33 SCU, 10-7 rotate on specific EOI, 8-33...
  • Page 510 INDEX port 2, 13-6 rotate instructions, A-10 port 3, 13-7 shift instructions, A-9 programming, 13-7–13-12 string instructions, 2-22–2-23, A-2 registers, 13-7–13-11 INT instruction, single-byte‚ See Breakpoint reset status, 13-11 interrupt I/O space, 3-1–3-7 INT0 instruction, 2-43 accessing, 3-6 INTA bus cycle‚ See Bus cycles reserved locations, 2-15, 6-14 Integer, defined, 2-37, 14-7 Idle mode, 5-11–5-16, 5-16...
  • Page 511 INDEX NMI, 2-42 reserved locations, 2-15 generating with WDT, 12-3 Memory devices‚ interfacing with, 3-6–3-7 nonmaskable, 2-44 Memory segments, 2-8 overview, 8-3 accessing, 2-5, 2-10, 2-11, 2-13 priority, 2-46–2-49, 8-4, 8-10–8-12 address automatic rotation, 8-12 base value, 2-10, 2-11, 2-12 fixed, 8-11 Effective Address (EA), 2-13 specific rotation, 8-11...
  • Page 512 INDEX exiting, 5-22 initialization code, 5-22–5-23 Packed BCD, defined, 2-37 Power-Save Register, 5-21 Packed decimal, defined, 14-7 Priority cell‚ See Interrupts Parity Flag (PF), 2-7, 2-9 Priority Resolver, 8-10 PCB Relocation Register, 4-1, 4-3, 4-6 Processor control instructions, 2-27 and math coprocessing, 14-1 Processor Status Word (PSW), 2-1, 2-7, 2-41 PDTMR pin, 5-18 bits defined, 2-7, 2-9...
  • Page 513 INDEX bus latency, 7-7 CTS# pin timings, 11-18 calculating refresh interval, 7-7 examples, 11-21–11-32 control registers, 7-7–7-10 features, 11-1 initialization code, 7-11 framing errors, 11-4 operation, 7-2 hardware considerations, 11-18–11-21 overview, 7-2–7-4 Interrupt Request Latch Register (SCUIRL), programming, 7-7–7-12 8-41 relationship to BIU, 7-1 interrupts, 11-21 Register operands, 2-27...
  • Page 514 INDEX SCU asynchronous mode, 11-21–11-22 SCU master/slave network, 11-24– Technical support, 1-6 11-32 Temporary real, defined, 14-7 initialization code, 11-26–11-28 Terminology _select_slave routine, 11-27–11-28 "above" vs. "greater", 2-26 _send_slave_command routine, "below" vs. "less", 2-26 11-32 device names, 1-2 _slave_1 routine, 11-29–11-31 Timer Control Registers (TxCON), 9-7, 9-8 SCU synchronous mode, 11-23 Timer Count Registers (TxCNT), 9-10...
  • Page 515 INDEX Trap exceptions, 2-42 Trap Flag (TF), 2-7, 2-9, 2-43, 2-48 T-state and bus cycles, 3-9 and CLKOUT, 3-8 defined, 3-7 Wait states and bus cycles, 3-13 and chip-selects, 6-11–6-14 and DRAM controllers, 7-1 and external 82C59A device, 8-46 and ICU, 8-44 and PCB accesses, 4-4 and READY input, 3-13 Watchdog Timer (WDT) Unit, 12-1–12-13...

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