EMBEDDED 32-BIT MICROPROCESSOR
WITH 16-BIT BURST DATA BUS
High-Performance Embedded
■
Architecture
— 20 MIPS* Burst Execution at 20 MHz
— 7.5 MIPS Sustained Execution
at 20 MHz
512-Byte On-Chip Instruction Cache
■
— Direct Mapped
— Parallel Load/Decode for Uncached
Instructions
Multiple Register Sets
■
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored
On-Chip
— Register Scoreboarding
The 80960SA is a member of Intel's i960
embedded applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960SA
has a large register set, multiple parallel execution units and a 16-bit burst bus. Using advanced RISC
technology, this high performance processor is capable of execution rates in excess of 7.5 million instructions
*
per second
. The 80960SA is well-suited for a wide range of cost sensitive embedded applications including
non-impact printers, network adapters and I/O controllers.
SIXTEEN
32-BIT GLOBAL
REGISTERS
512-BYTE
INSTRUCTION
INSTRUCTION
FETCH UNIT
CACHE
Figure 1. The 80960SA Processor's Highly Parallel Architecture
* Relative to Digital Equipment Corporation's VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment
Corporation)
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 2004
80960SA
Pin Compatible with 80960SB
■
Built-in Interrupt Controller
■
— 4 Direct Interrupt Pins
— 31 Priority Levels, 256 Vectors
Easy to Use, High Bandwidth 16-Bit Bus
■
— 32 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
32-Bit Address Space, 4 Gigabytes
■
80-Lead Quad Flat Pack (EIAJ QFP)
■
— 84-Lead Plastic Leaded Chip Carrier
Software Compatible with
■
80960KA/KB/CA/CF Processors
®
32-bit processor family, which is designed especially for low cost
64- BY 32-BIT
32-BIT
LOCAL
INSTRUCTION
REGISTER
EXECUTION
CACHE
UNIT
MICRO-
INSTRUCTION
INSTRUCTION
DECODER
SEQUENCER
August 2004
(PLCC)
32-BIT
BUS
CONTROL
MICRO-
LOGIC
INSTRUCTION
ROM
Order Number: 272206-003
32-BIT
ADDRESS
16-BIT
BURST
BUS