Entering Power-Save Mode - Intel 80C188EC User Manual

CLOCK GENERATION AND POWER MANAGEMENT
Possible clock divisor settings are 1 (undivided), 4, 8, 16, 32 and 64. The divided frequency feeds
the core, the integrated peripherals and CLKOUT. The processor operates at the divided clock
rate exactly as if the crystal or external oscillator frequency were lower by the same amount.
Since the processor is static, a lower limit clock frequency does not apply.
The advantage of Power-Save mode over Idle and Powerdown modes is that operation of both
the core and the integrated peripherals can continue. However, it may be necessary to reprogram
integrated peripherals such as the Timer Counter Unit and the Refresh Control Unit to compen-
sate for the overall reduced clock rate.
5.2.3.1

Entering Power-Save Mode

The Power-Save Register (Figure 5-14) controls Power-Save mode operation. The lower two bits
select the divisor. When program execution sets the PSEN bit, the processor enters Power-Save
mode. The internal clock frequency changes at the falling edge of T3 of the write to the Power-
Save Register. CLKOUT changes simultaneously and does not glitch. Figure 5-15 illustrates the
change at CLKOUT.
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