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CONTENTS
6.4
PROGRAMMING ........................................................................................................... 6-5
6.4.1
Initialization Sequence ..............................................................................................6-6
6.4.2
Start Address ..........................................................................................................6-10
6.4.3
Stop Address ..........................................................................................................6-10
6.4.4
Enabling and Disabling Chip-Selects ......................................................................6-11
6.4.5
Bus Wait State and Ready Control .........................................................................6-11
6.4.6
Overlapping Chip-Selects .......................................................................................6-12
6.4.7
Memory or I/O Bus Cycle Decoding ........................................................................6-14
6.4.8
Programming Considerations ..................................................................................6-14
6.5
CHIP-SELECTS AND BUS HOLD............................................................................... 6-15
6.6
EXAMPLES ................................................................................................................. 6-15
6.6.1
Example 1: Typical System Configuration ..............................................................6-15
6.6.2
Example 2: Detecting Attempts to Access Guarded Memory .................................6-20
CHAPTER 7
REFRESH CONTROL UNIT
7.1
THE ROLE OF THE REFRESH CONTROL UNIT......................................................... 7-2
7.2
REFRESH CONTROL UNIT CAPABILITIES................................................................. 7-2
7.3
REFRESH CONTROL UNIT OPERATION.................................................................... 7-2
7.4
REFRESH ADDRESSES............................................................................................... 7-4
7.5
REFRESH BUS CYCLES .............................................................................................. 7-5
7.6
GUIDELINES FOR DESIGNING DRAM CONTROLLERS............................................ 7-5
7.7
PROGRAMMING THE REFRESH CONTROL UNIT..................................................... 7-7
7.7.1
Calculating the Refresh Interval ................................................................................7-7
7.7.2
Refresh Control Unit Registers .................................................................................7-7
7.7.2.1
Refresh Base Address Register ......................................................................7-8
7.7.2.2
Refresh Clock Interval Register .......................................................................7-8
7.7.2.3
Refresh Control Register .................................................................................7-9
7.7.2.4
Refresh Address Register .............................................................................7-10
7.7.3
Programming Example ...........................................................................................7-11
7.8
REFRESH OPERATION AND BUS HOLD.................................................................. 7-13
CHAPTER 8
INTERRUPT CONTROL UNIT
8.1
FUNCTIONAL OVERVIEW: THE INTERRUPT CONTROLLER ................................... 8-1
8.2
INTERRUPT PRIORITY AND NESTING....................................................................... 8-4
8.3
OVERVIEW OF THE 8259A ARCHITECTURE............................................................. 8-4
8.3.1
A Typical Interrupt Sequence Using the 8259A Module ...........................................8-6
8.3.2
Interrupt Requests ....................................................................................................8-9
8.3.2.1
Edge and Level Triggering ..............................................................................8-9
8.3.2.2
The Interrupt Request Register .......................................................................8-9
8.3.2.3
Spurious Interrupts ........................................................................................8-10
8.3.3
The Priority Resolver and Priority Resolution .........................................................8-10
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