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Register Name:
Register Mnemonic:
Register Function:
15
Bit
Bit Name
Mnemonic
M7:0
Mask IR
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 8-17. OCW1 — Interrupt Mask Register
Operation Command Word 1
OCW1 (accessed through MPICP1, SPICP1)
Interrupt Mask Register.
M
M
M
7
6
5
Reset
State
XXH
Setting a bit in the Interrupt Mask Register
inhibits the corresponding interrupt request line
from generating an interrupt. Clearing an M7:0
bit enables interrupts from the corresponding
source.
INTERRUPT CONTROL UNIT
0
M
M
M
M
M
4
3
2
1
0
A1225-0A
Function
8-31
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