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INPUT/OUTPUT PORTS
Register Name:
Register Mnemonic:
Register Function:
15
Bit
Mnemonic
PL7:0
Port Data
Latch 7:0
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be writ-
ten to a logic zero to ensure compatibility with future Intel products.
13.2.4 Port Pin State Register
The Port Pin State Register (Figure 13-7) is a read-only register that is used to determine the state
of a port pin. When the Port Pin State Register is read, the current state of the port pins is gated
to the internal data bus.
13-10
Port Data Latch Register
PxLTCH (P1LTCH, P2LTCH, P3LTCH)
Contains the data driven on pins programmed as
output ports.
Reset
Bit Name
State
FFH
Figure 13-6. Port Data Latch Register (PxLTCH)
P
P
P
P
L
L
L
L
7
6
5
4
Function
The data written to a PL bit appears on pins
programmed as general-purpose output ports.
NOTE: PL7 and PL6 do not exist for Port 3.
0
P
P
P
P
L
L
L
L
3
2
1
0
A1314-0A
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