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6.17 AC ELECTRICAL SPECIFICATIONS - SERIAL
COMMUNICATION PORT
(see Figure 6-15)
Num.
Characteristic
250
SPCLK Clock Output Period
251
SPCLK Clock Output Rise/Fall Time
252
Delay from SPCLK to Transmit (see Note 1)
253
SCP Receive Setup Time (see Note 1)
254
SCP Receive Hold Time (see Note 1)
NOTES:
1. This also applies when SPCLK is inverted by Cl in the SPMODE register.
2. The enable signals for the slaves may be implemented by the parallel 1/0 pins.
16 MHz
Unit
Min
Max
4
64
elks
-
15
ns
0
40
ns
40
-
ns
20
-
ns
6.18 AC ELECTRICAL SPECIFICATIONS - IDL TIMING
(All timing measurements,
unless, otherwise specified, are referenced to the L 1CLK at 50% point of VDDl (see Figure 6-16)
16 MHz
Num.
Characteristic
Unit
Min
Max
260
L 1CLK (IDL Clock) Frequency (see Note 1)
-
6.66
MHz
261
L1CLK Width Low
55
-
ns
262
L1CLK Width High
55
-
ns
263
L1TXD, L1RO, SDS1-SDS2 Rising/Falling Time
-
20
ns
264
L1SY1 (sync) Setup Time (to L1CLK Falling Edge)
30
-
ns
265
L 1 SY1 (sync) Hold Time (to L 1 CLK Falling Edge)
50
-
ns
266
L 1 SY1 (sync) Inactive Before 4th L 1 CLK
-
0
ns
267
L1TxD Active Delay (from L1CLK Rising Edge)
0
90
ns
268
L1TxD to High Impedance (from L1CLK Rising Edge) (see Note 2)
0
50
ns
269
L 1 RxD Setup Time (to L 1 CLK Falling Edge)
50
-
ns
270
L1RxD Hold Time (to L1CLK Falling Edge)
50
-
ns
271
Time Between Successive IDL sync
20
-
L1CLK
272
L1RQ Valid before Falling Edge of L1SY1
1
-
L1CLK
273
L 1GR Setup Time (to L 1SY1 Falling Edge)
50
-
ns
274
L1GR Hold Time (to L 1SY1 Falling Edge)
50
-
ns
275
SDS1-SDS2 Active Delay from L1CLK Rising Edge
10
90
ns
276
SDS 1-SDS2 Inactive Delay from L 1 CLK Falling Edge
0
=
ns
NOTES:
1. The ratio CLK/L 1 CLK must be greater than 2.5/1.
2. High impedance is measured at the 30% and 70% of VDD points, with the line at VDDl2 through 10K in parallel with
130 pF.
6-24
MC68302 USER'S MANUAL
MOTOROLA
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