Motorola MC68302 User Manual page 281

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6. Bus cycles, including arbitration, must be less than 10 clock cycles, which
implies no more than two wait states in system memory accesses.
7. At least two additional flags, for a total of four flags, must be inserted
between frames.
8. The SCP and SMC channels should not be utilized.
9. Multiple HO channels can be supported as long as they are not contig-
uous with respect to each other in the bit stream.
Concurrent operation of another
sec
in BISYNC, DDCMP, V.110, or as a
UART, even at slow data rates, will restrict the operation of the SCC operating
at the higher (HO or H11) rates.
Since operation at high data rates is characteristic of HDLC-framed channels
rather than BISYNC-, DDCMP-, or async-framed channels, the user can also
use the MC68302 in conjunction with either the Motorola MC68605 1984
CCITT X.25 LAPB controller or the MC68606 CCITI 0.921 Multilink LAPD
controller. Both of these devices fully support operation at T1/CEPT rates
(and above) and can operate with their serial clocks "gated" onto subchannels
of such an interface. These devices are full M68000 bus masters and perform
the full datalink layer protocol as well as support various transparent modes
within HDLC-framed operation .
MC68302 USER'S MANUAL
MOTOROLA