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6.20 AC ELECTRICAL SPECIFICATIONS -
PCM TIMING
Num.
300
301
302
303
304
305
306
307
308
309
310
311
NOTES:
There are two syncs types:
Short Frame - Sync signals are one clock cycle prior to the data
Long Frame -
Sync signals are N-bits that envelope the data, N>O
(see Figure 6-18)
Characteristic
L 1 CLK (PCM Clock) Frequency (see Note 1 I
L1CLK Width Low/High
L 1SYO-L1 SY1 Setup Time to L 1 CLK Falling Edge
L 1SYO-L1 SY1 Hold Time to L 1 CLK Falling Edge
L 1SYO-L1 SY1 Width Low
Time Between Successive Sync Signals (Short Frame)
L 1TxD Data Valid after L 1CLK Rising Edge (see Note 2)
L 1TxD to High Impedance (from L 1 CLK Rising Edge)
L 1 RxD Setup Time (to L 1 CLK Falling Edge)
L1RxD Hold Time (to L1CLK Falling Edge)
L 1TxD Data Valid After Syncs Rising Edge (Long) (see Note 21
L1TxD to High Impedance (from L1SYO-L1SY1 Falling Edge) (Long)
1. The ratio CLK/L 1 CLK must be greater than 2.511.
16 MHz
Min
Max
6.66
55
-
20
-
40
1
-
8
-
0
100
0
70
20
-
50
-
0
100
0
70
Unit
MHz
ns
ns
ns
L1CLK
L1CLK
ns
ns
ns
ns
ns
ns
2. L 1TxD becomes valid after the L 1CLK rising edge or the sync enable, whichever is later, if long frames are used.
6.21 AC ELECTRICAL SPECIFICATIONS -
NMSI TIMING
Num.
315
316
317
318
319
320
321
322
323
NOTE:
The NMSI mode uses two clocks, one for receive and one for transmit. Both clocks can be internal or external.
When the clock is internal, it is generated by the internal baud rate generator and it is output on L 1 RXD or L 1 TXD.
All the timing is related to the external clock pin. The timing is specified for NMSl1. It is also valid for NMS12 and
NMSl3.
(see Figure 6-19)
Internal Clock
External Clock
Characteristic
Unit
Min
Max
Min
Max
RCLK1 and TCLK1 Frequency (see Note 1)
-
5.12
-
6.668
MHz
RCLK1 and TCLK1 Low/High
70
-
55
-
ns
RCLK1 and TCLK1 Rise/Fall Time
-
20
-
20
ns
TxD1 Active Delay from TCLK1 Falling Edge
0
40
0
70
ns
RTS1 Active Delay from TCLK1 Falling Edge
0
40
0
100
ns
CTS1 Setup Time to TCLK1 Rising Edge
50
-
10
-
ns
RXD1 Setup Time to RCLK1 Rising Edge
50
-
10
-
ns
RXD1 Hold Time to RCLK1 Rising Edge
10
-
50
-
ns
CD1 Setup Time to RCLK1 Rising Edge
50
-
10
-
ns
1. The ratio CLK/TCLK1 and CLK/RCLK1 must be greater than 2.5/1 for external clock.
For internal clock the ratio must be greater than 3/1 (the input clock to the baud rate generator may be either CLK or
TIN1), in both cases the maximum frequency is limited to 16.67 MHz.
In asynchronous mode (UART), the bit rate is 1/16 of the clock rate.
MOTOROLA
MC68302 USER'S MANUAL
6-29
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