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MAIN
CLOCK
TIN1
RCS
EXTC
MUX
MUX
INTERNAL
RCLOCK
RCLK
PIN
DIV4
PRESCALER
DIVIDE BY
10R4
TCS
CD10-CDO
11-BIT
COUNTER
1·2048
MUX
INTERNAL
TCLOCK
Figure 4-6. SCC Baud Rate Generator
RCS - Receive Clock Source
Ta.K
PIN
The RCS bit selects either the baud rate generator output (RCS= 0) or the
external clock source on the RCLK pin (RCS= 1) for the receiver. If RCS= 0,
then the baud rate generator output is driven onto the RCLK pin.
After reset, RCLK defaults to an input and stays an input until a zero is
written to RCS.
CD10-CDO - Clock Divider
output clock rate. CD10-CDO are used to preset an 11-bit counter that is
decremented at the prescaler output rate. The counter is not otherwise
accessible to the user. When the counter reaches zero, it is reloaded with
the clock divider bits. Thus, a value of $7FF in CD10-CDO produces the
minimum clock rate (divide by 2048); a value of $000 produces the max-
imum clock rate (divide by 1 ).
Even when dividing by an odd number, the counter ensures a 50% duty
cycle by asserting the terminal count once on a clock high and next on a
clock low. The terminal count signals the counter expiration and toggles
the clock.
MOTOROLA
MC68302 USER'S MANUAL
4-21
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