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-------------------------------MC683o~~
1 GENERAL-
3TIMERS
INTERRUPT
PURPOSE
AND
RAM/ROM
CONTROLLER
OMA
ADDITIONAL
CHANNEL
FEATURES
1
1
1
~
68000
M68000
--
SYSTEM BUS
l
_..
CORE
,
6DMA
1152BYTES
DUAL-PORT
CHANNELS
RAM
"'
MICROCODED
'
COMMUNICATIONS
~
PERIPHERAL BUS
CONTROLLER
t
,
--
(RISC)
•
'
~
3SERIAL
OTHER
OTHER
SERIAL
CHANNELS
CHANNELS
PERIPHERALS
Figure 1-3. MC68302 System Design
buffers may be located in the on-chip RAM or in the off-chip system RAM.
Six DMA channels are dedicated to the six serial ports (receive and transmit
for each of the three
sec
channels). If data for an
sec
channel is programmed
to be located in the external RAM, the CP will program the corresponding
DMA channel for the required accesses, bypassing the dual-port RAM. If data
resides in the
dual-~nrt
RAM. th".!n
the
CP
at:i:-es!"e!" the
~.''\M
w!!h c:-:c
:::!c:::!~
cycle and no arbitration delays.
The use of a unique arbitration scheme and synchronous transfers between
microprocessor and dual-port RAM gives the appearance of zero wait-state
operation to the M68000 microprocessor core. The dual-port RAM can be
accessed by the CP main controller (RISC) once every clock cycle for either
read or write operations. When the M68000 core accesses the dual-port RAM,
each access is pipelined along with the CP accesses so that data is read or
written without conflict. The net effect is the loss of a single memory access
by the CP main controller per M68000 core access.
The buffer memory structure of the MC68302 can be configured to closely
match
1/0 channel requirements by careful selection of buffer size and buffer
MOTOROLA
MC68302 USER'S MANUAL
1-5
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