Motorola MC68302 User Manual page 165

Integrated multi-protocol processor
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4-62
I - Interrupt
1 =The M68000 core will be interrupted when this buffer has been used
by the HDLC controller.
0 =No interrupt is generated after this buffer has been used.
The following status bits are written by the HDLC controller after the received
data has been placed into the associated data buffer.
L -
Last in Frame
This bit is set by the HDLC controller when this buffer is the last in a frame.
This implies the reception of a closing flag or reception of an error, in which
case one or more of the CD, OV, AB, and LG bits are set. The HDLC controller
will write the number of frame octets to the data length field.
1 =This buffer is the last in a frame.
0 =This buffer is not the last in a frame.
F - First in Frame
This bit is set by the HDLC controller when this buffer is the first in a frame.
1 =The buffer is the first in a frame.
0 =The buffer is not the first in a frame.
Bits
9-6 -
Reserved for future use.
LG - Rx Frame Length Violation
A frame length greater than the maximum defined for this channel was
recognized (only the maximum-allowed number of bytes is written to the
data buffer).
NO - Rx Nonoctet Aligned Frame
A frame that contained a number of bits not exactly divisible by eight was
received.
AB - Rx Abort Sequence
A minimum of seven consecutive ones was received during frame recep-
tion.
CR -
Rx CRC Error
This frame contains a CRC error.
OV- Overrun
A receiver overrun occurred during frame reception.
MC68302 USER'S MANUAL
MOTOROLA

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