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6.9 AC ELECTRICAL SPECIFICATIONS - OMA
(see Figure 6-5)
16MHz
Num.
Characteristic
Symbol
Unit
Min
Max
80
OREO Asynchronous Setup Time (see Note 1)
tREQASI
15
-
ns
81
OREO Width Low (see Note 2)
tREQL
2
-
elk
82
OREO Low to BR Low (see Notes 3 and 4)
tREQLBRL
-
2
elk
83
Clock High to BR Low (see Notes 3 and 4)
tcHBRL
-
30
ns
84
Clock High to BR High Impedance (see Notes 3 and 4)
tCHBRZ
-
30
ns
85
BGACK Low to BR High Impedance (see Notes 3 and 4)
tBKLBRZ
30
-
ns
86
Clock High to BGACK Low
tcHBKL
-
30
ns
87
AS and BGACK High (the latest one) to BGACK Low
tABHBKL
1.5
2.5
elk
(when BG is Asserted)
+30
ns
88
BG Low to BGACK Low (No Other Bus Master)
tBGLBKL
1.5
2.5
elk
(see Notes 3 and 4)
+30
ns
89
BR High Impedance to BG High (see Notes 3 and 4)
tBRHBGH
0
-
ns
90
Clock on Which BGACK Low to Clock on Which AS Low
tcLBKLAL
2
2
elk
91
Clock High to BGACK High
tCHBKH
-
30
ns
92
Clock Low to BGACK High Impedance
tcLBKZ
-
15
ns
93
Clock High to DACK Low
tCHACKL
-
30
ns
94
Clock High to DACK High
tcHACKH
-
30
ns
95
Clock High to DONE Low
tCHDNL
-
30
ns
96
Clock Low to DONE High Impedance
tcHDNZ
-
30
ns
97
DONE Input Low to Clock High (Asynchronous Setup)
!Q..N.J.ID
-
15
ns
NOTES:
1. OREO is sampled on the falling edge of CLK in cycle steal and burst modes.
2. !f..!80 is satified for OREO, #81.._may be ignored.
3. BR will not be asserted while AS, HALT, or BEAR is asserted.
4. Specifications are for DISABLE CPU mode only.
5. OREO, DACK, and DONE do not apply to the SDMA channels.
6-10
MC68302 USER'S MANUAL
MOTOROLA
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