Motorola MC68302 User Manual page 188

4.5.13.14 PROGRAMMING THE BISYNC CONTROLLERS. There are two general
techniques that the software may employ to handle data received by the
BISYNC controllers. The simplest way is to allocate single-byte receive buff-
ers, request (in the status word in each BO) an interrupt on reception of each
buffer (i.e., byte), and implement the BISYNC protocol entirely in software
on a byte-by-byte basis. This simple approach is flexible and may be adapted
to any BISYNC implementation. The obvious penalty is the overhead caused
by interrupts on each received character.
A more efficient method is as follows. Multibyte buffers are prepared and
linked to the receive buffer table. Software is used to analyze the first (two
to three) bytes ofthe buffer to determine what type of block is being received.
When this has been determined, reception can continue without further in-
tervention to the user's software until a control character is encountered. The
control character signifies the end of the block, causing the software to revert
back to a byte-by-byte reception mode.
To accomplish this, the RCH bit in the BISYNC mask register should initially
be set, enabling an interrupt on every byte of data received. This allows the
software to analyze the type of block being received on a byte-by-byte basis.
After analyzing the initial characters of a block, the user should either set the
receiver transparent mode (RTR) bit in the BISYNC mode register or issue
the RESET BCS CALCULATION command. For example, if OLE-STX is re-
ceived, transparent mode should be entered. By setting the appropriate bit
in the BISYNC mode register, the BISYNC controller automatically strips the
leading OLE from <OLE-character> sequences. Thus, control characters are
only recognized when they follow a OLE character. The RTR bit should be
cleared after a OLE-ETX is received.
Alternatively, after receiving an SOH, the RESET BCS CALCULATION com-
mand should be issued. This command causes the SOH to be excluded from
BCS accumulation and the BCS to be reset. Note that the RBCS bit in the
BISYNC mode register (used to exclude a character from the BCS calculation)
is not needed here since SYNCs and leading DLEs (in transparent mode) are
automatically excluded by the BISYNC controller.
After recognizing the type of block above, the RCH interrupt should be masked.
Data reception then continues without further interruption of the M68000
core until the end of the current block is reached. This is defined by the
reception of a control character matching that programmed in the receive
control characters table.
MOTOROLA MC68302 USER'S MANUAL 4-85