Motorola MC68302 User Manual page 161

Integrated multi-protocol processor
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2. Clear To Send Lost (Collision) During Frame Transmission. When this
error occurs and the channel is not programmed to control this line with
software, the channel terminates buffer transmission, closes the buffer,
sets the CTS lost (CT) bit in the BD, and generates the TXE interrupt (if
enabled). The channel will resume transmission after the RESTART
TRANSMIT command is given.
NOTE
If this error occurs on the first or second buffer of the frame and the
retransmit enable (RTE) bit in the HDLC mode register is set, the
channel will retransmit the buffer when the CTS line becomes active
again. When working in ISDN mode with D-channel collision pos-
sibility, to ensure the retransmission method functions properly, the
first and second data buffers should contain more than 10 bytes of
data. The channel will also increment the retransmission counter
(RETRC) .
Reception Errors:
1. Overrun Error. The HDLC controller maintains an internal two-word FIFO
for receiving data. The CP begins programming the SDMA channel
(if
the data buffer is in external memory) and updating the CRC when the
first word is received in the FIFO. When a receive FIFO overrun occurs,
the channel writes the received data byte to the internal FIFO over the
previously received byte. The previous data byte and the frame status
are lost. Then the channel closes the buffer with the overrun (OV) bit
in the BD set and generates the RX interrupt (if enabled). The receiver
then enters the hunt mode.
2. Carrier Detect Lost During Frame Reception. When this error occurs and
the channel is not programmed to control this line with software, the
channel terminates frame reception, closes the buffer, sets the carrier
detect lost (CD) bit in the BD, and generates the RX interrupt (if enabled).
This error has the highest priority. The rest of the frame is lost, and
other errors are not checked in that frame. The receiver then enters the
hunt mode.
3. Abort Sequence. An abort sequence is detected by the HDLC controller
when seven or more consecutive ones are received. When this error
occurs, the channel closes the buffer by setting the Rx abort sequence
(AB) bit in the BD and generates the RX interrupt (if enabled). The
channel also increments the abort sequence counter (ABTSC). The CRC
and nonoctet error status conditions are not checked on aborted frames.
The receiver then enters hunt mode.
MC68302 USER'S MANUAL
MOTOROLA

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