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L1CLK
81
82
I
D
I
M
~
l1Rm~
81
82
I
D
I
M
~
•
'
I
J
t
SCC1-SCC3
SMC1
SMC2
(L1RQ and L1GR
not
san)
Example: 81 supporlll 2 bits, 82 supports 3 bits
L1TXD _ _ _
T_HR_E_E-S_!_AT_E _ _ __.
81
D
A
D
M
DON'TCARE
L1RXD
---------1
81
D
A
D
M
L1RXD
L1SY1
L1RO
L1GR
MOTOROLA
2
SCC2
SCC3
SMC1
2
SCC1
Figure 4-2. IDL Bus Signals
SCC1
SCC3
SMC2
IDL receive data; input to the IMP. Valid for the 20 bits of
the IDL; ignored for other signals that may be present.
IDL SYNC signal; input to the IMP. This signal indicates that
the 20 clock periods following the pulse designate the IDL
frame.
Request permission to transmit on the D channel; output
from the IMP.
Grant permission to transmit on the D channel; input to the
IMP.
MC68302 USER'S MANUAL
4-7
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