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4-18
controlling up to three independent full-duplex lines implementing bridges
or gateway functions or multiplexing up to three SCCs onto the same physical
layer interface to implement a 28
+
D ISDN basic rate channel or three chan-
nels of a PCM highway. Each protocol-type implementation uses identical
buffer structures to simplify programming.
The following protocols are supported: HDLC/SDLC, BISYNC, synchronous
and asynchronous DDCMP, UART, several transparent modes, and V.110 rate
adaption support. Each protocol can be implemented with IDL, GCI, PCM, or
NMSI physical layer interfaces (see 4.4 SERIAL CHANNELS PHYSICAL
INTERFACE) and can be configured to operate in either echo or loopback
mode. Echo mode provides a return signal from an SCC by retransmitting
the received signal. Loopback mode is a local feedback connection allowing
an SCC to receive the signal it is transmitting. (Echo and loopback mode for
multiplexed interfaces are discussed in 4.4 SERIAL CHANNELS PHYSICAL
INTERFACE).
The receive and transmit section of each SCC is supported with one of the
six dedicated SDMA channels (see 3.1 OMA CONTROL). These channels
transfer data between the SCCs and either external RAM or on-chip dual-
port RAM. This function is transparent to the user, being enabled and con-
trolled according to the configuration of each SCC channel. Each SCC can
be clocked by either an external source (with the clock pins RCLK or TCLK)
or by an internal source through a baud rate generator for each SCC channel.
The baud rate generator can derive its clock from the main IMP clock or from
a separate input clock.
The SCCs exhibit two types of performance limitations. The first type is a
hardware clocking limit, which is the same for each SCC. The SCC clocks
must not exceed a ratio of 1 :2.5 serial clock (RCLK or TCLK) to parallel clock
(EXTAL). Thus, for a 16.67-MHz system clock frequency, the serial clock must
not exceed 6.67 MHz. The second type concerns the system data rate. The
SDMA channels and CP main controller must have enough time to service
the SCCs, thus preventing FIFO underruns and overruns in the SCCs. This
requirement depends on a number of factors discussed in more detail in
APPENDIX A
sec
PERFORMANCE.
Each SCC supports the standard seven-line modem interface (also referred
to as NMSI) with the signals RXD, TXD, RCLK, TCLK, RTS, CTS, and CD. Other
modem signals (such as DSR and DTR) may be supported through the parallel
1/0 pins. A block diagram of the SCC is depicted in Figure 4-5.
MC68302 USER'S MANUAL
MOTOROLA
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