Motorola MC68302 User Manual page 145

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2. Carrier Detect Lost During Character Reception. When this error occurs
and the channel is not programmed to control this line with software,
the channel terminates character reception, closes the buffer, sets the
carrier detect lost (CD) bit in the BD, and generates the RX interrupt (if
enabled). This error's priority is the highest; the last character in the
buffer is lost and other errors are not checked.
3. Framing Error. Framing error is reported by the UART controller when
no stop bit is detected in a received data string. When this error occurs,
the channel writes the received character to the buffer, closes the buffer,
sets framing error (FR) in the BD, and generates the RX interrupt (if
enabled). The channel also increments the framing error counter
(FRMEC). When this error occurs, parity is not checked for this character.
4. Parity Error. When the parity ermr occurs, the channel writes the re-
ceived character to the buffer, closes the buffer, sets parity error (PR)
in the BD, and generates the RX interrupt (if enabled). The channel also
increments the parity error counter (PAREC).
5. Noise Error. Noise error is detected by the UART controller when the
three samples taken on every bit are not identical. When this error
occurs, the channel writes the received character to the buffer and pro-
ceeds normally but increments the noise error counter (NOSEC).
6. IDLE Sequence. Receive IDLE (preamble) is detected by the UART con-
troller when a character with 9 to 13 consecutive ones (depending on
the ML TD, SL, PM, and CL bits in the UART mode register) is received.
When an IDLE sequence is received, the channel starts to count the
number of IDLE sequences received. If it reaches the MAX-IDL value,
the buffer is closed and an RX interrupt is generated (if enabled).
7. BREAK Sequence. A BREAK sequence is detected by the UART receiver
when a character with zero value and framing error is received. When
a BREAK sequence is received, the channel will increment the BRKEC
counter and generate a BRK interrupt (if enabled). If the channel was in
the middle of buffer processing, the buffer is closed and an RX is gen-
erated (if enabled).
Error Counters
The UART maintains four 16-bit modulo-2**16) error counters for the
receive portion of each UART controller. These free-running counters are
MC68302 USER'S MANUAL
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