Ac Electrical Characteristics - Motorola PowerPC 603 Hardware Specifications

1.4.2 AC Electrical Characteristics

This section provides the AC electrical characteristics for the 603. After fabrication, parts are sorted by
maximum processor core frequency as shown in Section 1.4.2.1, "Clock AC Specifications" and tested for
conformance to the AC specifications for that frequency. The processor core frequency is determined by the
bus (SYSCLK) frequency and the settings of the PLL_CFG[0–3] signals. PLL_CFG signals should be set
prior to power up and not altered afterwards. These specifications are for 66 MHz core frequency with
33 MHz bus (66C—2:1 bus mode), 66 MHz bus (66A—1:1 bus mode), and 80 MHz core frequency with
40 MHz bus (80C—2:1 bus mode). Parts are sold by maximum processor core frequency and bus mode; see
Section 1.9, "Ordering Information."
1.4.2.1 Clock AC Specifications
Table 6 provides the clock AC timing specifications as defined in Figure 1.
Vdd = 3.3 ± 5% V dc, GND = 0 V dc , 0 ≤ T
Num Characteristic
Processor frequency
VCO frequency
SYSCLK (bus) frequency
1 SYSCLK cycle time
2,3 SYSCLK rise and fall time
4 SYSCLK duty cycle measured at 1.4 V
SYSCLK jitter
603 internal PLL-relock time
Notes:
1. Caution : The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective
maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in Section 1.8,
"System Design Information," for valid PLL_CFG[0–3] settings, and to Section 1.9, "Ordering Information," for
available frequencies and part numbers.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under ± 150 ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the
power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum
of 255 bus clocks after the PLL-relock time (100 µs) during the power-on reset sequence.
603 Hardware Specifications
Table 6. Clock AC Timing Specifications
≤ 105 ° C
j
66C
Min Max
16.67 66.0
120 240
16.67 33.0
40.0 60.0
— 2.0
40.0 60.0
± 150
—
— 100
66A 80C
Min Max Min
16.67 66.0 16.67
120 240 120
16.67 66.0 16.67
30.0 60.0 25.0
— 2.0 —
40.0 60.0 40.0
± 150
— —
— 100 —
Unit Notes
Max
80.0 MHz 1
240 MHz
40.0 MHz
60.0 ns
2.0 ns 2
60.0 % 3
± 150
ps 4
µ s
100 3, 5
7