Motorola MC68302 User Manual page 115

4-12
The IMP supports all five channels of the GCI channel 0. The following table
shows where each channel can be routed. The two B channels can be con-
catenated and routed to the same
sec
channel.
GCI Channel 0 Serial Controllers
D
scc1,scc2,scc3
81
SCC1, SCC2, SCC3
82 SCC1,SCC2,SCC3
M
SMC1
C/I
SMC2
The GCI interface supports the CCITI 1.460 recommendation for data rate
adaptation. The GCI interface can access each bit of the B channel as an
8-kbps channel. The mask register (SIMASK) for the B channels specifies
which bits are supported by the GCI interface. The receiver will receive only
the bits that are enabled by SIMASK; the transmitter will transmit only the
bits that are enabled by SI MASK and will not drive the L 1TXD pin otherwise
(L 1TXD in GCI mode is an open-drain output).
The IMP supports contention detection on the D channel. When the IMP has
data to transmit on the D channel, it checks bit 4 of the SCIT C/I channel 2.
The physical layer device monitors the physical layer bus for activity on the
D channel and indicates with this bit that the channel is free. If a collision is
detected on the D channel, the physical layer device sets bit 4 of C/I channel
2 to logic high. The IMP then aborts its transmission and retransmits the
frame when this bit is asserted again. This procedure is handled automatically
for the first two buffers of a frame. The L 1 GR line may also be used for access
to the S interface D channel. This signal is checked by the IMP, and the
physical layer device should indicate that the S interface D channel is free
by asserting L1GR.
In the deactivated state, the clock pulse is disabled, and the data line is a
logic one. The layer-1 device activates the IMP by enabling the clock pulses
and by an indication in the channel 0 C/I channel. The IMP will then report
to the M68000 core by a maskable interrupt that a valid indication is in the
SMC2 receive buffer descriptor.
When the M68000 core activates the line, it sets SETZ in the serial interface
mode (SI MODE) register, causing the data output from L 1TXD to become a
logic zero. Code 0 (command timing TIM) will be transmitted on channel 0
C/I channel to the layer-1 device until the SETZ is reset. The physical layer
device will resume transmitting the clock pulses and will give an indication
in the channel 0 C/I channel. The M68000 core should reset SETZ to enable
data output.
MC68302 USER'S MANUAL
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