Motorola MC68302 User Manual page 96

WPVE - Write Protect Violation Enable
0 = BERR is not asserted when a write protect violation occurs.
1 = BERR is asserted when a write protect violation occurs.
After system reset, this bit defaults to zero.
NOTE
WPV will be set, regardless of the value of WPVE.
RMCST - RMC Cycle Special Treatment
1 =The read-modify-write cycles will be identical to the M68000 RMC
cycles (AS will be asserted during the entire cycle). The arbiter will
issue BG, regardless of the M68000 core RMC.
1 =The MC68302 uses RMC to negate AS at the end of the read portion
of the RMC cycle and assert AS at the beginning of the write portion.
The assertion of the RMC by the M68000 core is seen by the arbiter and
will prevent the arbiter from issuing bus grants until the completion of
M68000-initiated RMC activity. After system reset, this bit defaults to zero.
EMWS - External Master Wait State
When EMWS is set and an external master is using the chip-select logic
for DTACK generation or is accessing the internal peripherals, one addi-
tional wait state will be inserted in that memory cycle. When EMWS is
cleared, the internal access will be with zero wait states, and the chip-select
logic will generate DTACK after the programmed number of wait states.
The chip-select lines are asserted slightly earlier for internal master mem-
ory cycles than for an external master. EMWS should be set whenever
these timing differences will necessitate an additional wait state for external
masters. After svstem reset. this bit defaults to zero.
ADCE - Address Decode Conflict Enable
0 =BEAR is not asserted by a conflict in the chip-select logic when two
or more chip-select lines are programmed to overlap the same area.
1 = BERR is asserted by a conflict in the chip-select logic when two or
more chip-select lines are programmed to overlap the same area.
After system reset, this bit defaults to zero.
NOTE
ADC will be set, regardles of the value of ADCE.
MOTOROLA
MC68302 USER'S MANUAL 3-49