Motorola MC68302 User Manual page 66

terrupts are encoded on the IPL2-IPLO lines. In the dedicated mode, EXRO
interrupts are presented directly as IRQ7, IR06, and IR01.
Normal Mode
In this mode, the three interrupt request pins are configured as IPL2-IPLO.
Up to seven levels of interrupt priority may be implemented in the IMP
system. Level 4 is reserved for IMP INRO interrupts and may not be gen-
erated by an external device.
Dedicated Mode
In this mode, the three interrupt request pins are configured as IR07, IRQ6,
and IR01 to provide dedicated request lines for three external sources.
Each of these lines is programmed to be edge-triggered or level-sensitive.
In addition to level 4, which is reserved for INRO interrupts, interrupt priority
levels 2, 3, and 5 must not be assigned to external devices in this mode.
In systems that use the dedicated mode, the user may program the port B
control register (PBCNT) to select the dedicated on-chip peripheral functions
for IACK7, IACK6, IACK1 (normally PB2-PBO). Dedicated interrupt acknowl-
edge signals eliminate the need for external logic to perform the decoding
of the A 19-A 16, A3-A 1, and FC2-FCO pins and allow an external device to
detect an interrupt acknowledge cycle. By selecting the dedicated mode for
the interrupt controller and correctly programming PBCNT, the user can cre-
ate three interrupt request/interrupt acknowledge pairs.
The interrupt controller also prioritizes both INRQ and EXRO interrupts for
handling by the M68000 core. All INRO interrupt sources are assigned a fixed
priority level (level 4). The system designer assigns each EXRO interrupt to
an appropriate priority level so that pending interrupts are serviced according
to their relative importance. If more than one interrupt reauest is oending.
the interrupt controller presents the highest priority interrupt. A priority en-
coder combines EXRO requests and INRO requests to deliver IPL2-IPLO to
the M68000 core.
In response to an interrupt request, the M68000 core executes an interrupt
acknowledge cycle. Interrupt latency can be improved by programming the
internal interrupt pending (IPEND) signal to assert the bus clear (BCLR) signal
and by using this signal to cause the current bus master to relinquish the
M68000 bus. During an interrupt acknowledge cycle, FC2-FCO are encoded
as 111, A3-A1 encode the priority level, and A19-A16 are driven high.
MOTOROLA
MC68302 USER'S MANUAL
3-19