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6.8 AC ELECTRICAL SPECIFICATIONS -
IMP BUS MASTER CYCLES
(see Figure 6-2, 6-3, and 6-4)
16 MHz
Num.
Characteristic
Symbol
Unit
Min
Max
6
Clock High to FC, Address Valid
tCHFCADV
-
45
ns
7
Clock High to Address, Data Bus High Impedance (Maximum)
tcHADZ
-
50
ns
8
Clock High to Address, FC Invalid (Minimum)
tcHAFI
0
-
ns
9
Clock High to AS, DS Asserted (see Note 1)
tcHSL
3
30
ns
11
Address, FC Valid to AS, DS Asserted (Read)/AS Asserted (Write)
tAFCVSL
15
-
ns
(see Note 2)
12
Clock Low to AS, DS Negated (see Note 1)
tcLSH
-
30
ns
13
AS, DS Negated to Address, FC Invalid (see Note 21
ts HA Fl
15
-
ns
14
AS (and DS Read) Width Asserted (see Note 21
tsL
120
-
ns
14A
DS Width Asserted, Write (see Note 2)
tDsL
60
-
ns
15
AS, DS Width Negated !see Note 2)
tsH
60
-
ns
16
Clock High to Control Bus High Impedance
tcHCZ
-
50
ns
17
AS, DS Negated to R/W Invalid (see Note 2)
tSHRH
15
-
ns
18
Clock High to R/W High (see Note 1)
tcHRH
-
30
ns
20
Clock High to R/W Low (see Note 1)
tCHRL
-
30
ns
20A
AS Asserted to R!W Low (Write) (see Notes 2 and 6)
tASRV
-
10
ns
21
Address FC Valid to R!W Low (Write) (see Note 2)
tAFCVRL
15
-
ns
22
RIW Low to DS Asserted (Write) (see Note 2)
tRLSL
30
-
ns
23
Clock Low to Data-Out Valid
tcLDO
-
30
ns
25
AS, DS, Negated to Data-Out Invalid (Write) (see Note 2)
tSHDOI
15
-
ns
26
Data-Out Valid to DS Asserted (Write) (see Note 21
tDosL
15
-
ns
27
Data-In Valid to Clock Low (Setup Time on Read) (see Note 5)
tD1cL
7
-
ns
28
AS, DS Negated to DTACK Negated (Asynchronous Hold)
tSHDAH
0
110
ns
(see Note 2)
28A
Clock High to DTACK Negated
tCHDH
0
110
ns
29
AS, DS Negated to Data-In Invalid (Hold Time on Read)
tSHDll
0
-
ns
30
AS, DS Negated to BERR Negated
tSHBEH
0
-
ns
31
DTACK Asserted to Data-In Valid (Setup Time) (see Notes 2 and 5)
tDALDI
-
50
ns
32
HALT and RESET Input Transition Time
tRHr, tRHf
-
150
ns
33
Clock High to BG Asserted
tcHGL
-
30
ns
34
Clock High to BG Negated
tcHGH
-
30
ns
35
BR Asserted to BG Asserted
tBRLGL
2.5
4.5
elks
36
BR Negated to BG Negated (see Note 7)
tBRHGH
1.5
2.5
elks
37
BGACK Asserted to BG Negated
tGALGH
2.5
4.5
elks
37A
BGACK Asserted to BR Negated (see Note 8)
tGALBRH
10
1.5
ns/clks
38
BG Asserted to Control, Address, Data Bus High Impedance
tGLz
-
50
ns
(AS Negated)
39
BG Width Negated
IGH
1.5
-
elks
44
AS, DS Negated to AVEC Negated
tSHVPH
0
50
ns
- Continued
MOTOROLA
MC68302 USER'S MANUAL
6-5
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