Motorola MC68302 User Manual page 172

hunt mode when it is issued the ENTER HUNT MODE command, upon rec-
ognition of some error condition, or upon reception of an appropriately de-
fined control character.
When receiving data, the BISYNC controller updates the BCS bit (CR) in the
BO for every byte transferred. When the data buffer has been filled, the
Bl SYNC controller clears the empty (E) bit in the BO and generates an interrupt
if the interrupt (I) bit in the BD is set. If the incoming data exceeds the length
of the data buffer, the BISYNC controller will fetch the next BD in the table
and, if it is empty, will continue to transfer data to this BD's associated data
buffer.
When a BCS is received, it is checked and written to the data buffer. The
BISYNC controller sets the last bit, writes the message status bits into the
BD, and clears the empty bit. Then it generates a maskable interrupt, indi-
cating that a block of data has been received and is in memory. Note that
the SYN1-SYN2 pairs in the nontransparent mode or DLE-SYN1 pairs in the
transparent mode are not included in the BCS calculations.
The BISYNC controller may also be used to receive characters in a promis-
cuous (totally transparent) mode. See 4.5.9 SCC Transparent Mode Support.
4.5.13.3 BISYNC MEMORY MAP. When configured to operate in BISYNC mode,
the IMP overlays the structure illustrated in Table 4-5 onto the protocol-
specific area of that SCC parameter RAM. Refer to 2.8 MC68302 MEMORY
MAP for the placement of the three SCC parameter RAM areas and Table
4-2 for the other parameter RAM values.
The M68000 core configures each SCC to operate in one of four protocols
by the MODE 1-MODEO bits in the SCC mode register. MODE1-MODEO
=
11
selects the BISYNC mode of operation. The SYN1-SYN2 synchronization
characters are programmed in the data synchronization register (see 4.5.4
Data Synchronization Register (DSR)).
The BISYNC controller uses the same basic data structure as the UART, HDLC,
and DDCMP controllers. Receive and transmit errors are reported through
their respective BDs. The status of the line is reflected in the SCC status
register, and a maskable interrupt is generated upon each status change.
There are two basic ways of handling the BISYNC channels. First, data may
be inspected on a per-byte basis, with the BISYNC controller interrupting the
MOTOROLA
MC68302 USER'S MANUAL
4-69