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1--i
1--i
_.J
BASE REGISTER
J
L
1--i
Rfii
_,.J
COMPARE LOGIC
}
'
,..
,
_,.
_,.
_r
OPTION REGISTER
J
~
~i_
_,. ,
cso
l
CS1
1
CS2
"'
1
CS3
::i
CD
gs
w
"'
f
*
a:
~
Cl
[
l_
CD
5i!
DTACK GENERATION
~
I
-,.
Cl
Figure 3-6. Chip-Select Block Diagram
When a bus master attempts to write to a read-only location, the chip-select
logic will set write protect violation (WPV) in the SCR and generate BERR if
write protect violation enable (WPVE) is set. The CS line will not be asserted.
MOTOROLA
NOTE
The chip-select logic is reset only on total system reset (assertion of
RESET and HALT). Accesses to the internal RAM and registers, in-
cluding the system configuration registers (BAR and SCR), will not
activate the chip-select lines. The chip-select logic does not allow an
address match during interrupt acknowledge cycles.
MC68302 USER'S MANUAL
3-41
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