Motorola MC68302 User Manual page 181

Integrated multi-protocol processor
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RBCS -
Receive Block Check Sequence
The BISYNC receiver internally stores two BCS calculations with a byte
delay (eight serial clocks) between them. This enables the user to examine
a received data byte and then decide whether or not it should be part of
the BCS calculation. This is useful when control character recognition and
stripping is desired to be performed in software. The bit should be set (or
reset) within the time taken to receive the following data byte. When this
bit is reset, the BCS calculations exclude the latest fully received data byte.
When RBCS is set, the BCS calculations continue normally.
0 =Disable receive BCS
1 =Enable receive BCS
SYNF - Transmit
SYN1~SYN2
or IDLE between Messages and Control the
RTS Pin
0 =Send ones between messages; RTS is negated between messages.
The BISYNC controller can transmit ones in both NRZ and NRZI en-
coded formats.
1 =Send SYN1-SYN2 pairs between messages; RTS is always asserted.
ENC -
Data Encoding Format
0= Non-return to zero (NRZ). A one is a high level; a zero is a low level.
1 =Non-return to zero inverted (NRZI). A one is represented by no change
in the level; a zero is represented by a change in the level.
4.5.13.10 BISYNC RECEIVE BUFFER DESCRIPTOR (Rx BO}.
The CP reports infor-
mation about the received data for each buffer using BD. The Rx BD is shown
in Figure 4-15. The CP closes the current buffer, generates a maskable in-
terrupt, and starts to receive data into the next buffer after one of the following
events:
OFFSET+
0
OFFSET+
2
OFFSET+
4
OFFSET+
6
4-78
Receiving a user-defined control character
Detecting an error
Detecting a full receive buffer
Issuing the ENTER HUNT MODE command
15
14
13
12
11
10
E i x i w I
1
IcisI-I-I-I~I-I~I~l~Jwiw
DATA LENGTH
RX BUFFER POINTER
Figure 4-15. BISYNC Receive Buffer Descriptor
MC68302 USER'S MANUAL
MOTOROLA

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