Motorola MC68302 User Manual page 15

Integrated multi-protocol processor
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LIST OF ILLUSTRATIONS (Continued)
Figure
Number
Page
Title
Number
xii
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
HDLC Transmit Buffer Descriptor........................................... 4-63
BISYNC Control Characters Table.......................................... 4-73
BISYNC Receive Buffer Descriptor......................................... 4-78
Bl SYNC Transmit Buffer Descriptor........................................ 4-81
DDCMP Receive Buffer Descriptor......................................... 4-96
DDCMP Transmit Buffer Descriptor........................................ 4-99
Two-Step Synchronous Bit Rate Adaption.............................. 4-102
Three-Step Asynchronous Bit Rate Adaption . .. . .. . . . . .. .. . . . . . . .. . . . . 4-103
V.110 Receive Buffer Descriptor............................................. 4-106
V.110 Transmit Buffer Descriptor........................................... 4-107
5-1
Functional Signal Groups..................................................... 5-3
5-2
External Address/Data Buffer................................................ 5-8
6-1
Clock Timing Diagram .......................................................... 6-4
6-2
Read-Cycle Timing Diagram.................................................. 6-7
6-3
Write-Cycle Timing Diagram .. ... .. . . . . . . .. .. . . . . . . . . .. . . . . . . . .. . . . . . . .. . . . . . 6-8
6-4
Bus Arbitration Timing Diagram............................................ 6-9
6-5
DMA Timing Diagram.......................................................... 6-11
6-6
External Master Internal Read Cycle Timing Diagram..............
6-13
6-7
External Master Internal Read Cycle Timing Diagram
(One Wait State)............................................................... 6-14
6-8
External Master Internal Write Cycle Timing Diagram .............. 6-15
6-9
Internal Master Internal Read Cycle Timing Diagram............... 6-17
6-10
Internal Master Chip-Select Timing Diagram........................... 6-18
6-11
External Master Chip-Select Timing Diagram.......................... 6-20
6-12
Parallel 1/0 Data In/Data Out Timing Diagram ......................... 6-21
6-13
Interrupts Timing Diagram.................................................... 6-22
6-14
Timers Timing Diagram........................................................ 6-23
6-15
Serial Communication Port Timing Diagram ........................... 6-25
6-16
IDL Timing Diagram............................................................. 6-26
6-17
GCI Timing Diagram............................................................ 6-28
6-18
PCM Timing Diagram........................................................... 6-30
6-19
NMSI Timing Diagram.......................................................... 6-31
MC68302 USER'S MANUAL
MOTOROLA

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