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The RAM block diagram is shown in Figure 3-4. The M68000 core, the IDMA,
and the external master access the RAM through the IMP bus interface unit
(BIU) using the M68000 bus. When an access is made, the BIU generates a
wait signal to the CP main controller to prevent simultaneous access of the
RAM. The CP main controller waits for one cycle to allow the RAM to service
the M68000 bus cycle and then regenerates its RAM cycle. This mechanism
allows the RAM to be accessed synchronously by the M68000 core, IDMA,
or external master without wait states. Thus, during the four-clock M68000
memory cycle, three internal accesses by the CP main controller may occur.
The BIU also provides the DTACK signal output when the RAM and on-chip
registers are accessed.
SYSTEM RAM
576 BYTES
CP~CODE
AD RESS_,,.,
~
~§
CPµCODEDATA
_,,,
c~
~
Si!l}l
_,,,
(DATA RAM
OR
µCODE RAM)
I
I
~~
--""
PERIPHERAL
DATA BUS
INTERNAL
~
~
PERIPHERAL
ADDRESS
r1
BUS
Cl)
a:
'-----'
~
~t
--""
PARAMETER RAM
~~
576BYTES
_,,,
Si!l}l
..---
M68000
M68000
SYSTEM
DATA BUS
ADDRESS
""
~
BUS
,,_
~~""
--
~
.___
Figure 3-4. RAM Block Diagram
MOTOROLA
MC68302 USER'S MANUAL
3-33
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