Motorola MC68302 User Manual page 162

4. Nonoctet Aligned Frame. When this error occurs, the channel writes the
received data to the data buffer, closes the buffer, sets the Rx nonoctet
aligned frame (NO) bit in the BD, and generates the RX interrupt (if
enabled). The CRC error status is not checked on nonoctet frames. After
a nonoctet aligned frame is received, the receiver enters hunt mode.
(An immediately following back-to-back frame will be received.) The
nonoctet data may be derived from the last word in the data buffer as
follows:
MSB
LSB
LEADING ZEROS
VALID DATA
NOT VALID DATA
5. CRC Error. When this error occurs, the channel writes the received CRC
to the data buffer, closes the buffer, sets the CR bit in the BD, and
generates the RX interrupt (if enabled). The channel also increments the
CRC error counter (CRCEC). After receiving a frame with a CRC error,
the receiver enters hunt mode. (An immediately following back-to-back
frame will be received.) CRC checking cannot be disabled, but the CRC
error may be ignored if checking is not required.
Error Counters
The CP maintains five 16-bit (modulo-2**16) error counters for each HDLC
controller. These free-running counters are cleared to zero at reset. They
can be written by the user when the channel is disabled. The counters are
as follows:
MOTOROLA
DISFC- Discarded Frame Counter (error-free frames but no free buffers)
CRCEC - CRC Error Counter
ABTSC - Abort Sequence Counter
NMARC - Nonmatching Address Received Counter (error-free frames
only)
RETRC - Frame Retransmission Counter (due to collision)
MC68302 USER'S MANUAL