Motorola MC68302 User Manual page 170

The BISYNC controller consists of separate transmit and receive sections
whose operations are asynchronous with the M68000 core and may be either
synchronous or asynchronous with respect to the other SCCs. Each clock can
be supplied from either the internal baud rate generator or from external
pins. More information on the baud rate generator is available in 4.5.2 SCC
Configuration Register (SCON).
The main BISYNC controller features are as follows:
• Flexible Data Buffers
• Eight Control Character Recognition Registers
• Automatic SYNC1 and SYNC2 Detection
• SYNC/DLE Stripping and Insertion
• CRC16 and LRC Generation/Checking
• Parity (VRC) Generation/Checking
• Supports BISYNC Transparent Operation (Use of DLE Characters)
• Supports Promiscuous (Totally Transparent) Reception and
Transmission
• Maintains Parity Error Counter
• External SYNC Support
• Reverse Data Mode
• Four Commands
4.5.13.1 BISYNC CHANNEL FRAME TRANSMISSION PROCESSING. The BISYNC
transmitter is designed to work with almost no intervention from the M68000
core. When the M68000 core enables the BISYNC transmitter, it will start
transmitting SYN1-SYN2 pairs (located in the data synchronization register)
or idle as programmed in the BISYNC mode register. The BISYNC controller
polls the first buffer descriptor (BD) in the transmit channel's BD table. When
there is a message to transmit, the Bl SYNC controller will fetch the data from
memory and start transmitting the message (after first transmitting the
SYN1-SYN2 pair).
When a BD's data has been completely transmitted, the last in message (L)
bit is checked. If both the L bit is set, and transmit BCS bit are set in that BD,
the BISYNC controller will append the CRC16/LRC. Subsequently, the Bl SYNC
controller writes the message status bits into the BD and clears the ready
MOTOROLA MC68302 USER'S MANUAL
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