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WSC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
WWS — Write Wait State
This bit is used to determine if an additional wait state is required for write cycles.
This is useful for writing to Flash memories that require additional data setup time.
0 = Reads and writes are the same length.
1 = An additional wait state is inserted for write cycles unless WSC is set to
1111. Setting WSC to 1111 results in 16-clock transfers regardless of the
WWS bit. Read cycles are not affected.
EDC — Extra Dead Cycle
This bit is used to determine if an idle cycle is inserted after a read cycle for back-to-
back external transfers to eliminate data bus contention. This is useful for slow mem-
ory and peripherals.
0 = Back-to-back external transfers occur normally, i.e., no idle cycle is inserted
after a read cycle.
1 = An idle cycle is inserted after a read cycle for back-to-back external
transfers, unless the next cycle is a read cycle to the same CS bank.
CSA — Chip Select Assert
This bit is used for devices that require additional address setup time and additional
address/data hold times. It determines when the chip select is asserted and whether
an idle cycle is inserted between back-to-back external transfers. If WSC=0000, this
bit is ignored.
0 = Chip select is asserted normally, i.e., as early as possible. No idle cycle is
inserted between back-to-back external transfers.
1 = Chip select is asserted a clock later during both read and write cycles. In
addition, an idle cycle is inserted between back-to-back external transfers.
MOTOROLA
C-18
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
Table C-6 Wait State Control Field Settings
Number of Wait States
WWS = 0
Read Access Write Access Read Access Write Access
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
WWS = 1
0
0
1
1
2
2
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7
7
8
8
9
9
10
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14
15
15
1
2
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MMC2001
REFERENCE MANUAL
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