Interface Requirements For Read And Write Cycles - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

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The port size is programmable via the DSZ bits in the corresponding CS control reg-
ister. In addition, the portion of the data bus used for transfer to or from an 8-bit port is
programmable via the same bits. An 8-bit port can reside on external data bus bits
DATA[15:8] or DATA[7:0].
A word access to or from an 8-bit port requires four bus cycles to complete the trans-
fer. A word access to or from a 16-bit port requires two bus cycles to complete the
transfer. A halfword access to or from an 8-bit port requires two bus cycles to com-
plete the transfer. In the case of a multi-cycle transfer, the lower two address bits,
ADDR[1:0], are incremented appropriately.
The EIM data multiplexer takes the four bytes of the CPU interface data bus and
routes them to their required positions to interface properly to memory and peripher-
als.
Table 7-2 lists the combination of TSIZ, ADDR[1:0] signals and DSZ bits that are
used for each possible transfer size, alignment, and port width. The bytes labeled with
a dash are not required; they are ignored on read transfers and driven with undefined
data on write transfers.
Table 7-2 Interface Requirements for Read and Write Cycles
Signal Encoding
Transfer
Size
TSIZ1 TSIZ0 ADDR1 ADDR0
Byte
0
1
Halfword
1
0
Word
0
0
MMC2001
REFERENCE MANUAL
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Port Width
DSZ[1:0]
00
0
0
01
10
00
0
1
01
10
00
1
0
01
10
00
1
1
01
10
00
0
x
01
10
00
1
x
01
10
00
x
x
01
10
EXTERNAL INTERFACE MODULE
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Active Interface Bus Sections (Internal)
DATA[31:24] DATA[23:16] DATA[15:8]
DATA[15:8]
DATA[7:0]
DATA[15:8]
DATA[15:8]
DATA[7:0]
DATA[7:0]
DATA[15:8]
DATA[15:8]
DATA[7:0]
DATA[7:0]
DATA[15:8]
DATA[7:0]
DATA[15:8]
DATA[15:8]
DATA[7:0]
DATA[7:0]
DATA[15:8]
DATA[7:0]
DATA[7:0]
DATA[15:8]
DATA[7:0]
DATA[15:8]
DATA[15:8]
DATA[7:0]
DATA[7:0]
DATA[15:8]
DATA[15:8]
DATA[7:0]
DATA[7:0]
DATA[15:8]
DATA[7:0]
DATA[15:8]
DATA[15:8]
DATA[7:0]
DATA[7:0]
DATA[15:8]
DATA[7:0]
MOTOROLA
7-5

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