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12.4.3 ISPI Interval Control Register
The ISPI interval control register (SPICR) controls interval mode operation.
SPICR — ISPI Interval Control Register
15
14
13
12
R
0
LPBK IVL_EN
W
RESET:
0
0
0
LPBK — Loopback
This bit enables a loopback test feature in the ISPI. When looping back, the ISPI
operates as if the SPI_MISO and SPI_MOSI pins are wired together and there are no
other external devices connected to the ISPI data input pin. Whenever loopback is
enabled, the data read from the ISPI data register after a given transfer matches what
was written to the ISPI data register prior to that transfer, masked if necessary to
account for the number of bits transferred.
0 = Loopback disabled
1 = Loopback enabled
IVL_EN — Interval Mode Enable
Setting this bit places the ISPI in interval mode. If the MSTR bit in the ISPI control
register is cleared, then the ISPI is operating in slave mode, and this bit is ignored.
0 = ISPI is not operating in interval mode
1 = ISPI is operating in interval mode if MSTR=1
INTERVAL COUNT
In interval mode, this register value is loaded into the ISPI interval timer upon comple-
tion of a transfer. Each bit-clock period, the value in this counter is decremented by
one. When the value in the register reaches zero, then XCH is set, and a new transfer
is begun.
12.4.4 ISPI Status Register
The ISPI status register (SPSR) contains flags indicating whether an overrun condi-
tion has occurred, whether an interrupt has been requested, and whether a transfer is
being performed.
SPSR — ISPI Status Register
15
14
13
12
R
OVR
IRQ
XCH
W
RESET:
0
0
0
MOTOROLA
12-8
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Freescale Semiconductor, Inc.
11
10
9
0
0
0
0
Figure 12-5 ISPI Interval Control Register
11
10
9
0
0
0
0
0
0
0
0
Figure 12-6 ISPI Status Register
INTERVAL MODE SERIAL PERIPHERAL INTERFACE
For More Information On This Product,
Go to: www.freescale.com
8
7
6
5
INTERVAL COUNT
0
0
0
0
8
7
6
5
0
0
0
0
0
0
0
0
10008004
4
3
2
1
0
0
0
0
10008006
4
3
2
1
0
0
0
0
0
0
0
0
MMC2001
REFERENCE MANUAL
0
0
0
0
0
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