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The alternate file is selected for use via a control bit in the PSR. The status, control,
and scratch registers are accessed via the move from control register (mfcr) and
move to control register (mtcr) instructions. When the alternate file is selected via the
AF bit in the PSR, general-purpose operands are accessed from it. When the AF bit
is cleared, operands are accessed from the normal file. This alternate file is provided
to allow very low overhead context switching capability for real-time event handling.
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
PC
User Programmer's
Model
The supervisor programming model includes the PSR, which contains operation con-
trol and status information. In addition, a set of exception shadow registers is pro-
vided to save the state of the PSR and the program counter at the time an exception
occurs. A separate set of shadow registers is provided for fast interrupt support to
minimize context saving overhead.
Five scratch registers are provided for supervisor software use in handling exception
events. A single register is provided to alter the base address of the exception vector
table. Two registers are provided for global control and status.
MOTOROLA
2-4
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Freescale Semiconductor, Inc.
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
PC
C
Supervisor Programmer's
Figure 2-1 Programming Model
INTEGER CPU
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Alternate file
R0'
R1
R2
PSR
R3
VBR
R4
EPSR
R5
FPSR
R6
EPC
R7
FPC
R8
SS0
R9
SS1
R10
SS2
R11
SS3
R12
SS4
R13
GCR
R14
GSR
R15
* bit 0 of PSR
C
Model
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
CR8
CR9
CR10
CR11
CR12
MMC2001
REFERENCE MANUAL
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