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bit, as the load occurs on the next rising PCLK edge following internal synchroniza-
tion. Forcing a load of the comparator latches and counter in this manner must be
done with caution to avoid unexpected pin behavior.
DATA — PWM Data
This bit indicates or controls the current state of the PWM pin. When the pin is config-
ured as a general-purpose output, the logical value written to this bit is used to drive
the pin. When the pin is configured as a general-purpose input, the pin value is
reflected by this bit. When the pin is configured in PWM mode, the bit reflects the
value being driven on the pin by the PWM logic.
DIR — Direction
This bit controls the direction of the pin when used as a GPIO pin. This bit has no
effect when MODE indicates PWM mode.
0 = Pin is an input pin
1 = Pin is an output pin
POL — Polarity
This bit controls the polarity of the pin when used as a PWM output pin. Normally, the
output pin is set high at period boundaries and goes low when a width compare event
occurs.
This bit is ignored if the pin is being used as a GPIO pin.
0 = Normal PWM polarity
1 = Inverted PWM polarity
MODE — PWM Mode
This bit selects whether the PWM pin is used for GPIO or for the PWM function.
0 = General-purpose I/O mode
1 = PWM mode
COUNT EN — Counter Enable
This bit enables or disables the PWM counter. The counter is actually enabled or dis-
abled some time after the CPU writes this bit. It is enabled on the next rising PCLK
edge following internal synchronization. If running, the counter is disabled following
the next period match.
0 = PWM disabled. While disabled, the counter is in a low-power mode and does
not count. The following events occur:
When the output pin is configured to operate in PWM mode (MODE = 1), the
output pin is forced to the setting of the POL bit.
The counter is reset to 00 and frozen.
The contents of the width and period registers are loaded into the compara-
tors.
The comparators are disabled.
If the counter has been running, and the actual disable occurs at the occur-
rence of a period match, an interrupt request may still be generated, even
though the counter is being disabled. To prevent this, write the interrupt
enable control bit (IRQ_EN) to zero when disabling the counter.
MMC2001
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
PULSE WIDTH MODULATOR
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
15-5
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