Watchdog Timer; Tod Fraction Alarm Register; Watchdog Timer Block Diagram - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

TODFAR — TOD Fraction Alarm Register
31 30 29 28
R

TOD FRACTION ALARM REGISTER

W
RESET:
Undefined on POR
15 14 13 12
R 0 0 0
W
RESET:

9.5 Watchdog Timer

The watchdog timer is used to protect against system failures by providing a means
of escape from unexpected events or programming errors. Once started, the watch-
dog timer must be serviced by software on a periodic basis. If servicing does not take
place, the watchdog times out and asserts a reset signal.
WSTP (one-time write)
STOP (from CPU)*
WDZE (one-time write)
DOZE (from CPU)*
WDBG (one-time write)
DBUG (from CPU)*
WDE (one-time write)
(From Clock Block)
* NOTE: DOZE and STOP are generated from the CPU signals LPMD1 and LPMD0
DBUG is an active high signal from the CPU indicating debug mode
MOTOROLA
9-8
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Freescale Semiconductor, Inc.
27 26 25
11 10 9
0 0 0 0
Figure 9-8 TOD Fraction Alarm Register
2 Hz
Figure 9-9 Watchdog Timer Block Diagram
TIMER/RESET MODULE
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24 23 22 21
0 0 0
8 7 6 5
0 0 0 0
Watchdog Service Register (WSR)
Watchdog Control Register (WCR)
6-Bit Counter
10001014
20 19 18 17
0 0 0 0
4 3 2 1
0 0 0 0
Reset
Underflow
MMC2001
REFERENCE MANUAL
16
0
0
0