Table of Contents
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1-1
MMC2001 Block Diagram ................................................................................ 1-2
2-1
Programming Model......................................................................................... 2-4
2-2
Data Organization in Memory .......................................................................... 2-5
2-3
Data Organization in Registers ........................................................................ 2-5
2-4
Signal Relationships to Clocks......................................................................... 2-9
2-5
M•CORE Bus Signals .................................................................................... 2-10
2-6
External Multiplexer Connections................................................................... 2-13
4-1
Functional Signal Groups................................................................................. 4-1
7-1
EIM Block Diagram .......................................................................................... 7-1
7-2
EIM Interface to Memory and Peripherals........................................................ 7-4
7-3
CS0 Control Register ....................................................................................... 7-7
7-4
CS1, CS2, CS3 Control Registers ................................................................... 7-8
7-5
EIM Configuration Register ............................................................................ 7-11
7-6
Read Memory Access (CSA = 0, WSC = 1)................................................... 7-14
7-7
Write Memory Access (CSA = 0, WSC = 1, WWS = 0) ................................. 7-15
7-8
Word Read Access from Halfword Width Memory......................................... 7-16
7-9
Word Write Access to Halfword Width Memory ............................................. 7-17
7-10 Write after Read Memory Access (CSA = 0, WSC = 2, EDC = 0) ................. 7-18
7-11 Write after Read Memory Access (CSA = 0, WSC = 1, EDC = 1) ................. 7-19
7-12 Peripheral Read Access (CSA = 1, WSC = 5) ............................................... 7-20
7-13 Peripheral Write Access (CSA = 1, WSC = 5) ............................................... 7-21
7-14 Read and Write Fast Memory Access (CSA = 0, WSC = 0, WWS = 0)......... 7-22
8-1
MMC2001 Clock Module.................................................................................. 8-3
9-1
Reset Functional Block Diagram...................................................................... 9-2
9-2
Reset Source Register ..................................................................................... 9-3
9-3
TOD Block Diagram ......................................................................................... 9-4
9-4
TOD Control/Status Register ........................................................................... 9-5
9-5
TOD Seconds Register .................................................................................... 9-6
9-6
TOD Fraction Register ..................................................................................... 9-7
9-7
TOD Seconds Alarm Register.......................................................................... 9-7
9-8
TOD Fraction Alarm Register........................................................................... 9-8
9-9
Watchdog Timer Block Diagram ...................................................................... 9-8
9-10 Watchdog Control Register ............................................................................ 9-10
9-11 Watchdog Service Register............................................................................ 9-11
9-12 PIT Block Diagram ......................................................................................... 9-12
9-13 Starting a Count from an Off State................................................................. 9-12
9-14 Counter Reloading from the Modulus Latch................................................... 9-13
9-15 Counter in Free-Running Mode...................................................................... 9-13
9-16 PIT Control and Status Register .................................................................... 9-14
9-17 PIT Data Register........................................................................................... 9-15
9-18 PIT Alternate Data Register ........................................................................... 9-16
10-1 Interrupt Source Register ............................................................................... 10-2
10-2 Normal Interrupt Enable Register................................................................... 10-3
MMC2001
REFERENCE MANUAL
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Freescale Semiconductor, Inc.
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