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EPPAR — Edge Port Pin Assignment Register
15
14
13
12
R
EPPA7
EPPA6
W
RESET:
0
0
0
0
Figure C-28 Edge Port Pin Assignment Register
EPPAx — Edge Port Pin Assignment Select Field x
Pins configured as level-sensitive are inverted so that a logic low on the external pin
represents a valid interrupt request. Level-sensitive interrupt inputs are not latched.
To guarantee that a level-sensitive interrupt request is acknowledged, the interrupt
source must keep the signal asserted until acknowledged by software.
Pins configured as edge-sensitive interrupts are latched for interrupt generation pur-
poses and need not remain asserted for interrupt generation. When the pin is pro-
grammed to use the edge detecting circuit, its state is monitored regardless of its
configuration as input or output.
These bits are cleared by hardware reset.
C.7.2 Edge Port Data Direction Register (EPDDR)
The 16-bit read/write edge port data direction register (EPDDR) controls the direction
of the port pins. Setting any bit in this register configures the corresponding pin as an
output. Clearing any bit in this register configures the corresponding pin as an input.
Pin direction is independent of the level/edge mode programmed.
EPDDR — Edge Port Data Direction Register
15
14
13
12
R
0
0
0
0
W
RESET:
Figure C-29 Edge Port Data Direction Register
MOTOROLA
C-28
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Freescale Semiconductor, Inc.
11
10
9
8
EPPA5
EPPA4
0
0
0
0
Table C-13 EPPAx Field Settings
Value
00
Pin INTx defined as level sensitive
01
Pin INTx defined as rising edge detect
10
Pin INTx defined as falling edge detect
Pin INTx defined as both falling and rising
11
edge detect
11
10
9
8
0
0
0
0
PROGRAMMING REFERENCE
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7
6
5
4
EPPA3
EPPA2
0
0
0
0
Meaning
7
6
5
4
EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 EPDD0
0
0
0
0
10007000
3
2
1
0
EPPA1
EPPA0
0
0
0
0
10007002
3
2
1
0
0
0
0
0
MMC2001
REFERENCE MANUAL
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