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The MMC2001 integrated processor incorporates the following functional units:
• M•CORE™ Integer Processor
— 32-bit RISC architecture
— Low power, high performance
• On-chip, 256-Kbyte ROM
• On-chip, 32-Kbyte SRAM with battery backup supply support
• Interrupt Controller
— Support for up to 32 interrupt sources
• External Interface Module (EIM)
— Transfers information between the MMC2001 and external memory or periph-
erals
— 22 address lines
— 16 data lines
— Chip select and wait state generation
— Bus watchdog timer
• Timer/Reset Module
— Crystal oscillator: generates the master clock signal for the time-of-day timer
from a 32.768-kHz external crystal
— Time-of-day timer: provides time-of-day information as well as an alarm clock
function
— Watchdog timer: resets the chip to recover from system failure
— Reset unit: provides low voltage detection input and backup power switching
for SRAM and the time-of-day timer
— Periodic interrupt timer
• Universal Asynchronous Receiver/Transmitter Module (UART)
— Two independent UART channels
— Asynchronous operation
— Baud rate generation
— Infrared (IR) interface support
• 16-bit general-purpose I/O port with support for keyboard scan/encode
• 8-bit general-purpose I/O port with support for edge/level sensitive external inter-
rupts
• Pulse-Width Modulation Module (PWM)
— Six independent PWM channels
— Programmable period
— Programmable duty cycle
— Periodic interrupt capability
— Pins can be configured as general-purpose I/O
• Interval Mode Serial Peripheral Interface (ISPI)
— Efficient communication with slower serial peripherals
MMC2001
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
SECTION 1
INTRODUCTION
INTRODUCTION
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
1-1
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