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WP — Write Protect
This bit is used to restrict writes to the address range defined by the corresponding
chip select.
0 = Writes are allowed in this chip select address space.
1 = Writes are prohibited. An attempt to write to an address mapped by this chip
select will result in a TEA to the CPU and no assertion of the chip select
output.
PA — Pin Assert
This bit is used to control the chip select pin when it is operating as a programmable
output pin (i.e. the CSEN bit clear). This bit is ignored if the CSEN bit is set. At reset,
PA bit is set for CS[1:2] and cleared for CS3.
0 = Brings chip select output to logic-low level
1 = Brings chip select output to logic-high level
CSEN — Chip Select Enable
This bit controls the operation of the chip select pin.
0 = Chip select function is disabled. An attempted access to an address mapped
by this chip select will result in TEA assertion to the CPU and no assertion of
the chip select output.
When disabled, the pin is a general-purpose output controlled by the
value of the PA control bit. When CSEN0 is clear, CS0 is inactive.
1 = Chip select is enabled and is asserted when an access address falls within
the range specified in Table C-8. With the exception of CS0, this bit is
cleared by reset, disabling the chip select output pin.
CSEN0 is set at reset to allow CS0 to select from an external boot ROM if MOD is
driven to a logic-low level four LOW_REFCLK clock cycles before RSTOUT negation.
When the chip select is enabled, the PA control bit is ignored.
C.5.2 EIM Configuration Register
The EIM configuration register contains control bits that configure the EIM and other
internal blocks for certain operation modes.
Access this register with 32-bit loads and stores only.
MOTOROLA
C-20
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
Table C-8 Chip-Select Address Range
ADDR[31:24]
—
00101101
00101111
00101110
00101100
PROGRAMMING REFERENCE
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Go to: www.freescale.com
Chip Select
Inactive
CS0
CS1
CS2
CS3
REFERENCE MANUAL
MMC2001
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