Pit Alternate Data Register (Itadr); Pit In Low-Power Modes; Pit In Debug Mode; Pit Alternate Data Register - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

9.6.7 PIT Alternate Data Register (ITADR)

The PIT alternate data register is a read-only register that provides access to the
counter value. Access this register with 32-bit loads and stores only.
ITADR — PIT Alternate Data Register
31 30 29 28
R 0 0 0 0
W
RESET:
15 14 13 12
R
W
RESET:

9.6.8 PIT in Low-Power Modes

The PIT is unaffected by wait mode. In stop or doze mode, the timer may either con-
tinue to run or be halted. If the DOZE or STOP bit is set in the control/status register,
the timer is halted in the respective mode. When doze or stop mode is exited, timer
operation reverts to what it was prior to entering doze or stop mode.

9.6.9 PIT in Debug Mode

In debug mode, the module may either continue to run or be halted. If the DBG bit is
set in the PIT control/status register, the timer is halted. When debug mode is exited,
the timer operation reverts to what it was prior to entering debug mode.
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27 26 25 24
0 0 0 0
11 10 9 8
PIT COUNTER
Figure 9-18 PIT Alternate Data Register
TIMER/RESET MODULE
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23 22 21 20
0 0 0 0
7 6 5 4
1000102C
19 18 17 16
0 0 0 0
3 2 1 0
MMC2001
REFERENCE MANUAL